Erratum to: Circuits Syst Signal Process DOI 10.1007/s00034-014-9887-1
In the original publication, the affiliation “Member IEEE” of the authors has been erroneously tagged as a third author in the article. This has been corrected with this erratum.
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The online version of the original article can be found under doi:10.1007/s00034-014-9887-1.
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Safaei Mehrabani, Y., Eshghi, M. Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology. Circuits Syst Signal Process 34, 761 (2015). https://doi.org/10.1007/s00034-015-9968-9
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DOI: https://doi.org/10.1007/s00034-015-9968-9