Skip to main content
SpringerLink
Log in

A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

In this paper, a power- and area-efficient, multirate, Quasi-cyclic, low-density, parity-check decoder is proposed. The proposed decoder design is based on a simplified adaptive normalized min-sum algorithm. The proposed algorithm effectively utilizes two correction factors for check-node and variable-node update processes. This corrects the channel errors at relatively low signal-to-noise ratio. In order to reduce the finite word length effects, a six-bit nonuniform quantization with the overlapped message passing scheme is used. In addition, an improved early termination scheme is also used to reduce the total number of decoding iterations. This reduces the overall power consumption of the decoder. The simulations have been carried out using Xilinx ISE 14.1 and implemented on Virtex 5 FPGA. The proposed decoder is synthesized using CADENCE with UMC 130 nm technology. With a core area of 1.16 mm\(^{2}\), the proposed decoder achieves a maximum throughput of 3.4 Gb/s for 15 decoding iterations with a power dissipation of 114.3 mW.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9

Similar content being viewed by others

References

  1. V.A. Chandrasetty, S.M. Aziz, FPGA implementation of a LDPC decoder using a reduced complexity message passing algorithm. J. Netw. 6(1), 36–45 (2011)

    Google Scholar 

  2. M.A. Chao et al., Matrix merging scheme and efficient decoding techniques for reconfigurable QC-LDPC decoders. J. Signal Process. Syst. 68(2), 183–202 (2012)

    Article  Google Scholar 

  3. Y.H. Chen, et al., A Channel-Adaptive Early Termination strategy for LDPC decoders, in Proceedings of IEEE Workshop on Signal Processing Systems, Oct 2009, pp. 226–231

  4. J. Chen, M.P.C. Fossorier, Near-optimum universal belief-propagation-based decoding of low-density-parity check codes. IEEE Trans. Commun. 50(3), 406–414 (2002)

    Article  Google Scholar 

  5. J. Chen et al., Construction of irregular LDPC codes by quasi-cyclic extension. IEEE Trans. Inf. Theory 53(4), 1479–1483 (2007)

    Article  Google Scholar 

  6. K. Cushon et al., A min-sum iterative decoder based on pulsewidth message encoding. IEEE Trans. Circuits Syst. II 57(11), 893–897 (2010)

    Article  Google Scholar 

  7. Y. Dai et al., Optimal overlapped message passing decoding of quasi-cyclic LDPC codes. IEEE Trans. VLSI Syst. 16(5), 565–578 (2008)

    Article  Google Scholar 

  8. M.P.C. Fossorier et al., Reduced complexity iterative decoding of low density parity check codes based on belief propagation. IEEE Trans. Commun. 47(5), 673–680 (1999)

    Article  MathSciNet  Google Scholar 

  9. R.G. Gallager, Low-density parity-check codes. IRE Trans. Inf. Theory IT–8, 21–28 (1962)

    Article  MathSciNet  Google Scholar 

  10. K. Gunnam, et al., Multi-rate Layered Decoder Architecture for Block LDPC Codes of IEEE 802.11n Wireless Standard, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), May 2007, pp. 1645–1648

  11. D.E. Hocevar, A Reduced Complexity Decoder Architecture via Layered Decoding of LDPC Codes, in Proceedings of IEEE Workshop on Signal Processing Systems, Austin, TX, Oct 2004, pp. 107–112

  12. IEEE, IEEE Standard 802.11n-2009, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications—Amendment 5: Enhancement for Higher Throughput, (IEEE, 2009)

  13. IEEE, IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Broadband Wireless Access Systems, IEEE Std 802.16-2009 (Revision of IEEE Std 802.16-2004), (IEEE, 2009).

  14. N.S. Jayant, Waveform Quantization and Coding (IEEE Press Selected Reprint Series) (John Wiley & Sons Canada limited, Mississauga, 1976)

    Google Scholar 

  15. J. Jin, C. Tsu, Improving the Hardware Utilization Efficiency of Partially Parallel LDPC Decoder with Scheduling and Sub-matrix Decomposition, in Proceedings of IEEE International Symposium on Circuits and Systems, May 2009, pp. 2233–2236

  16. M. Karkooti et al., Configurable, high throughput, irregular LDPC decoder architecture: tradeoff analysis and implementation, in Proceedings of IEEE international conference on Application Specific Systems, Architectures and Processors, Sept 2006, pp. 360–367

  17. L. Liu, C.J.R. Shi, Sliced message passing: high throughput overlapped decoding of high-rate low-density parity-check codes. IEEE Trans. Circuits Syst.-I 55(11), 3697–3710 (2008)

    Article  MathSciNet  Google Scholar 

  18. M.G. Luby et al., Improved low-density parity-check codes using irregular graphs. IEEE Trans. Inf. Theory 47(2), 585–598 (2001)

    Article  MATH  MathSciNet  Google Scholar 

  19. T. Mohsenin et al., A low-complexity message-passing algorithm for reduced routing congestion in LDPC decoders. IEEE Trans. Circuits Syst. I 57(5), 1048–1061 (2010)

    Article  MathSciNet  Google Scholar 

  20. D. Oh, K.K. Parhi, Min-sum decoder architectures with reduced word length for LDPC codes. IEEE Trans. Circuits Syst.-I 57(1), 105–115 (2010)

    Article  MathSciNet  Google Scholar 

  21. N. Onizawa et al., Design of high-throughput fully parallel LDPC decoders based on wire partitioning. IEEE Trans. VLSI Syst. 18(3), 482–489 (2010)

    Article  Google Scholar 

  22. T.J. Richardson et al., Design of capacity-approaching irregular low-density parity check codes. IEEE Trans. Inf. Theory 47(2), 619–637 (2001)

    Article  MATH  Google Scholar 

  23. T.J. Richardson, R.L. Urbanke, The capacity of low-density parity check codes under message passing decoding. IEEE Trans. Inf. Theory 47(2), 599–618 (2001)

    Article  MATH  MathSciNet  Google Scholar 

  24. C. Roth, et al., A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS, in Proceedings IEEE Asian Solid State Circuits Conference, Nov 2010, pp. 1–4

  25. X.Y. Shih, et al., A 7.39 mm\(^{2}\) 76 mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications, in Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC), 2008, pp. 301–304

  26. Y. Sun, et al., Multi-layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-cyclic LDPC Codes, in Proceedings of IEEE International Symposium on Circuits and Systems, May 2011, pp. 1776–1779

  27. X. Wu et al., Adaptive-normalized/offset min-sum algorithm. IEEE Commun. Lett. 14(7), 667–669 (2010)

    Article  Google Scholar 

  28. B. Xiang et al., An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes. IEEE Trans. VLSI Syst. 18(10), 1447–1460 (2010)

    Article  Google Scholar 

  29. J. Zhang, M.P.C. Fossorier, A modified weighted bit-flipping decoding of low-density parity-check codes. IEEE Commun. Lett. 8(3), 165–167 (2004)

    Article  Google Scholar 

  30. J. Zhang et al., Two-dimensional correction for min-sum decoding of irregular LDPC codes. IEEE Trans. Commun. Lett. 10(3), 180–182 (2006)

    Article  Google Scholar 

  31. C. Zhang et al., Flexible LDPC decoder design for multigigabit-per-second applications. IEEE Trans. Circuits Syst.-I 57(1), 116–124 (2010)

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, PSG College of Technology, Peelamedu Post, Coimbatore, 641004, Tamil Nadu, India

    Michaelraj Kingston Roberts & Ramesh Jayabalan

Authors
  1. Michaelraj Kingston Roberts
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Ramesh Jayabalan
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Michaelraj Kingston Roberts.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Roberts, M.K., Jayabalan, R. A Power- and Area-Efficient Multirate Quasi-Cyclic LDPC Decoder. Circuits Syst Signal Process 34, 2015–2035 (2015). https://doi.org/10.1007/s00034-014-9949-4

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-014-9949-4

Keywords

Search

Navigation