Skip to main content
Log in

Combinatorial constructions of optimal low-power error-correcting cooling codes

  • Published:
Designs, Codes and Cryptography Aims and scope Submit manuscript

Abstract

High temperatures have dramatic negative effects on interconnect performance. In a bus, whenever the state transitions from “0” to “1”, or “0” to “1”, joule heating causes the temperature to rise. A low-power error-correcting cooling (LPECC) code, introduced in Chee et al. (IEEE Trans Inf Theory 64:3062–3085, 2018), is a coding scheme which can be used to control the peak temperature, the average power consumption of on-chip buses and error-correction for the transmitted information, simultaneously. In this paper, we show upper bounds and some lower bounds of LPECC codes by some combinatorial configurations, and also present several families of optimal LPECC codes.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Bao J., Ji L.: The completion determination of optimal \((3,4)\)-packings. Des. Codes Cryptogr. 77, 217–229 (2015).

    Article  MathSciNet  Google Scholar 

  2. Benini L., De Micheli G., Macii E., Sciuto D., Silvano C.: Asymptotic zero-transition activity encoding for address busses in lowpower microprocessor-based systems. In: Proceedings of the \(7\)th Great Lakes Symposium on VLSI (GLSVLSI), Urbana-Champaign, IL, USA, May 1997, pp. 77–82 (1997).

  3. Chee Y.M., Colbourn C.J., Ling A.C.H.: Optimal memoryless encoding for low power off-chip data buses. In: Proceedings of the International Conference on Computer-Aided Design (ICCAD), November 2006, pp. 369–374 (2006).

  4. Chee Y.M., Etzion T., Kiah H.M., Vardy A.: Cooling codes: thermal-management coding for high-performance interconnects. IEEE Trans. Inf. Theory 64, 3062–3085 (2018).

    Article  MathSciNet  Google Scholar 

  5. Chee Y.M., Etzion T., Kiah H.M., Vardy A., Wei H.: Low-power cooling codes with efficient encoding and decoding. IEEE Trans. Inf. Theory 66, 4804–4818 (2020).

    Article  MathSciNet  Google Scholar 

  6. Colbourn C.J., Dinitz J.H. (eds.): The CRC Handbook of Combinatorial Designs, 2nd edn CRC Press, Boca Raton (2007).

    Google Scholar 

  7. Hanani H.: Balanced incomplete block designs and related designs. Discret. Math. 11, 255–369 (1975).

    Article  MathSciNet  Google Scholar 

  8. Komatsu S., Fujita M.: Irredundant address bus encoding techniques based on adaptive codebooks for low power. In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Huntington Beach, CA, USA, August 2001, pp. 9–14 (2001).

  9. Macii E., Pedram M., Somenzi F.: High-level power modeling, estimation, and optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17, 1061–1079 (1998).

    Article  Google Scholar 

  10. Petrov P., Orailoglu A.: Low-power instruction bus encoding for embedded processors. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12, 812–826 (2004).

    Article  Google Scholar 

  11. Sithambaram P., Macii A., Macii E.: New adaptive encoding schemes for switching activity balancing in on-chip buses. In: Proceedings of the 17th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Gothenburg, Sweden, September 2007, pp. 232–241 (2007).

  12. Sotiriadis P.P., Chandrakasan A.P.: Reducing bus delay in submicron technology using coding. In: Proceedings of the IEEE Asia and South Pacific Design Automation Conference, February 2001, pp. 109–114 (2001).

  13. Sotiriadis P.P., Chandrakasan A.P.: Bus energy reduction by transition pattern coding using a detailed deep submicrometer bus model. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 50, 1280–1295 (2003).

    Article  Google Scholar 

  14. Sotiriadis P.P., Wang A., Chandrakasan A.P.: Transition pattern coding: an approach to reduce energy in interconnect. In: Proceedings of the ISSCIRC, Stockholm, Sweden, September 2000, pp. 348–351 (2000).

  15. Stan M.R., Burleson W.P.: Bus-invert coding for low-power I/O. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 3, 49–58 (1995).

    Article  Google Scholar 

  16. Sundaresan K., Mahapatra N.R.: Accurate energy dissipation and thermal modeling for nanometer-scale buses. In: Proceedings of the 11th International Symposium on High-Performance Computer Architecture (HPCA), February 2005, pp. 51–60 (2005).

  17. Wang F., De Bole M., Wu X., Xie Y., Vijaykrishnan N., Irwin M.J.: On-chip bus thermal analysis and optimisation. IET Comput. Digit. Technol. 1, 590–599 (2007).

    Article  Google Scholar 

Download references

Acknowledgements

The authors are very grateful to the referees and Editor for their valuable suggestions and helpful comments that improved the quality of this paper.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Shuangqing Liu.

Ethics declarations

Conflict of interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Additional information

Communicated by M. Buratti

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Supported by the National Natural Science Foundation of China under Grant 12101440, the Natural Science Foundation of Jiangsu Province under Grant BK20210858 (Liu), and the National Natural Science Foundation of China under Grant 12271390 (Ji).

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Liu, S., Ji, L. Combinatorial constructions of optimal low-power error-correcting cooling codes. Des. Codes Cryptogr. (2024). https://doi.org/10.1007/s10623-024-01391-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • DOI: https://doi.org/10.1007/s10623-024-01391-0

Keywords

Mathematics Subject Classification

Navigation