Abstract
This paper proposes a full-transistor multilevel delay element (DE) implemented by 65 nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to realize the fine-grain and coarse tuning for multilevel delay adjustment while maintain the duty cycle of input pulse. In physical design, a novel transistor array with a compact regularity layout is adopted to mitigate process variation. According to the post-layout simulation analysis, compared with two traditional delay elements, the proposed DE has particular advantages in terms of the layout area as well as achieves the acceptable merely 2× power consumption and 22.9% delay quantization error in linearity accuracy. The effective 2 MHz bandwidth and nano-second delay range is applicable to a low/medium frequency clock compensation system.
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Acknowledgements
This work was partially supported by the National Natural Science Foundation of China (NSFC, Grant Nos. 61704049, 61804046), the Key Scientific Research Projects of Higher Education Institutions in Henan Province (Grant No. 19A510012), the Foundation of Department of Science and Technology of Henan Province (Grant Nos. 182102210295, 192102210087, 202102210322).
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Liu, B., Huang, Zh., Zhang, Jc. et al. A full-transistor fine-grain multilevel delay element with compact regularity layout. Analog Integr Circ Sig Process 103, 163–172 (2020). https://doi.org/10.1007/s10470-020-01588-y
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DOI: https://doi.org/10.1007/s10470-020-01588-y