Abstract
This chapter starts by highlighting the requirements and existing techniques in producing digital delay, summarizing the state of the art. Subsequently, a topology assessment is presented based on specified performance metrics. The proposed delay cell which was designed, fabricated, and characterized is then described. Specifically, the proposed design is based on a topology with low-supply-noise sensitivity and low jitter. Functionality is extended to support coarse/fine control for the output delay value, without the need for additional hardware. This is made possible by taking advantage of the body-biasing capabilities available in FD-SOI technology. The proposed delay element presents unique performance characteristics in terms of the achieved delay resolution and delay dynamic range. The chapter concludes with the demonstration of a delay line prototype, fabricated in ST 28 nm FD-SOI technology. After a general overview of delay techniques the proposed topology is described, by focusing on the major design aspects. Measurement results are then presented and a short discussion follows on the characterization findings.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
M. Hossain, F. Aquil, P.S. Chau, B. Tsang, P. Le, J. Wei, T. Stone, et al., A fast-lock, jitter filtering all-digital DLL based burst-mode memory interface. IEEE J. Solid-State Circuits 49(4), 1048–62 (2014). https://doi.org/10.1109/JSSC.2013.2297403
L. Xu, S. Lindfors, K. Stadius, J. Ryynanen, A 2.4-GHz low-power all-digital phase-locked loop. IEEE J. Solid-State Circuits 45(8), 1513–21 (2010). https://doi.org/10.1109/JSSC.2010.2047453
I.J. Chang, S.P. Park, K. Roy, Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE J. Solid-State Circuits 45(2), 401–10 (2010). https://doi.org/10.1109/JSSC.2009.2036764
J.-P. Jansson, A. Mäntyniemi, J. Kostamovaara, A CMOS time-to-digital converter with better than 10 ps single-shot precision. IEEE J. Solid-State Circuits 41(6), 1286–96 (2006). https://doi.org/10.1109/JSSC.2006.874281
J.-R. Su, T.-W. Liao, C.-C. Hung, Delay-line based fast-locking all-digital pulsewidth-control circuit with programmable duty cycle, in 2012 IEEE Asian Solid State Circuits Conference (A-SSCC) (IEEE, Piscataway, 2012), pp. 305–8. https://doi.org/10.1109/IPEC.2012.6522686
C. Vezyrtzis, W. Jiang, S.M. Nowick, Y. Tsividis, A flexible, clockless digital filter, in 2013 Proceedings of the ESSCIRC (ESSCIRC) (2013), pp. 65–68. https://doi.org/10.1109/ESSCIRC.2013.6649073
Y.W. Li, K.L. Shepard, Y.P. Tsividis, A continuous-time programmable digital FIR filter. IEEE J. Solid-State Circuits 41(11), 2512–20 (2006). https://doi.org/10.1109/JSSC.2006.883314
J.M. Rabaey, A.P. Chandrakasan, B. Nikolić, Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall Electronics and VLSI Series (Prentice Hall, Upper Saddle River, 2003)
M. Bazes, A novel precision MOS synchronous delay line. IEEE J. Solid-State Circuits 20(6), 1265–71 (1985). https://doi.org/10.1109/JSSC.1985.1052467
M. Maymandi-Nejad, M. Sachdev, A digitally programmable delay element: design and analysis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 11(5), 871–78 (2003). https://doi.org/10.1109/TVLSI.2003.810787
L.H. Jung, N. Shany, A. Emperle, T. Lehmann, P. Byrnes-Preston, N.H. Lovell, G.J. Suaning, Design of safe two-wire interface-driven chip-scale neurostimulator for visual prosthesis. IEEE J. Solid-State Circuits 48(9), 2217–29 (2013). https://doi.org/10.1109/JSSC.2013.2264136
M. Maymandi-Nejad, M. Sachdev, A monotonic digitally controlled delay element. IEEE J. Solid-State Circuits 40(11), 2212–19 (2005). https://doi.org/10.1109/JSSC.2005.857370
J.-L. Yang, C.-W. Chao, S.-M. Lin, Tunable delay element for low power VLSI circuit design, in TENCON 2006 - 2006 IEEE Region 10 Conference (2006), pp. 1–4. https://doi.org/10.1109/TENCON.2006.344092
A. Sekiyama, T. Seki, S. Nagai, A. Iwase, N. Suzuki, M. Hayasaka, A 1-V operating 256-kb full-CMOS SRAM. IEEE J. Solid-State Circuits 27(5), 776–82 (1992). https://doi.org/10.1109/4.133168
N.R. Mahapatra, A. Tareen, S.V. Garimella, Comparison and analysis of delay elements, in The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002, vol. 2 (2002), pp. II-473–II-476. https://doi.org/10.1109/MWSCAS.2002.1186901
J. Zhang, S.R. Cooper, A.R. LaPietra, M.W. Mattern, R.M. Guidash, E.G. Friedman, A low power thyristor-based CMOS programmable delay element, in Proceedings of the 2004 International Symposium on Circuits and Systems ISCAS ’04, vol. 1 (2004), pp. I–769–72. https://doi.org/10.1109/ISCAS.2004.1328308
B. Schell, Y. Tsividis, A low power tunable delay element suitable for asynchronous delays of burst information. IEEE J. Solid-State Circuits 43(5), 1227–34 (2008). https://doi.org/10.1109/JSSC.2008.920332
B. Saft, E. Schafer, A. Jager, A. Rolapp, E. Hennig, An improved low-power CMOS thyristor-based micro-to-millisecond delay element, in ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC) (IEEE, Piscataway, 2014), pp. 123–126. https://doi.org/10.1109/ESSCIRC.2014.6942037
I. Sourikopoulos, A. Frappé, A. Kaiser, L. Clavier, A decision feedback equalizer with channel-dependent power consumption for 60-GHz receivers, in International Symposium in Circuits and Systems (ISCAS), Melbourne (IEEE, Piscataway, 2014), pp. 1484–87. https://doi.org/10.1109/ISCAS.2014.6865427
M. Kurchuk, C. Weltin-Wu, D. Morche, Y. Tsividis, Event-driven GHz-range continuous-time digital signal processor with activity-dependent power dissipation. IEEE J. Solid-State Circuits 47(9), 2164–73 (2012). https://doi.org/10.1109/JSSC.2012.2203459
I. Sourikopoulos, A. Frappé, A. Cathelin, L. Clavier, A. Kaiser, A digital delay line with coarse/fine tuning through gate/body biasing in 28nm FDSOI, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference (2016), pp. 145–48. https://doi.org/10.1109/ESSCIRC.2016.7598263
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Sourikopoulos, I., Cathelin, A., Kaiser, A., Frappé, A. (2020). Coarse/Fine Delay Element Design in 28 nm FD-SOI. In: Clerc, S., Di Gilio, T., Cathelin, A. (eds) The Fourth Terminal. Integrated Circuits and Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-39496-7_6
Download citation
DOI: https://doi.org/10.1007/978-3-030-39496-7_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-39495-0
Online ISBN: 978-3-030-39496-7
eBook Packages: EngineeringEngineering (R0)