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Low quiescent current capacitorless small gain stages LDO with controlled pass transistors

  • Mixed Signal Letter
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Abstract

A low quiescent current 180-nm output-capacitorless low-dropout regulator with small-gain stages (SGSs) is presented in this paper. The proposed technique permits the regulator to distribute the load current into two power transistors depending on the demand of the load using a controller based on load variation criterion. SGSs are introduced to enhance loop gain without low-frequency poles. The proposed architecture does not require compensation capacitor. Thus, the active chip area is reduced to 73.59 µm × 36 µm. The measured results have shown that the fabricated circuit consumes a quiescent current of 1.8 µA at no load, regulating the output at 1 V with maximum output current of 50 mA from a voltage supply of 1.2 V. It achieves full range stability from 0 to 50 mA load current at a maximum 100 pF load capacitor.

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Acknowledgements

This study was supported by a research fund from Chosun University 2016. The author would like to thank IC Design Education Center (IDEC), South Korea for supporting Cadence EDA tools and providing fabrication facility of Multi-Project Wafer (MPW) for Magna Chip/SK Hynix process 0.18 µm.

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Authors and Affiliations

  1. Institute of Sensors, Signals and Systems, School of Engineering and Physical Sciences, Heriot-Watt University, Edinburgh, UK

    Sadeque Reza Khan

  2. Department of Information and Communication Engineering, Chosun University, Gwangju, South Korea

    Iram Nadeem

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  1. Sadeque Reza Khan
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  2. Iram Nadeem
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Correspondence to Sadeque Reza Khan.

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Khan, S.R., Nadeem, I. Low quiescent current capacitorless small gain stages LDO with controlled pass transistors. Analog Integr Circ Sig Process 94, 323–331 (2018). https://doi.org/10.1007/s10470-017-1103-3

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  • DOI: https://doi.org/10.1007/s10470-017-1103-3

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