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A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

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Abstract

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm2. The receiver achieves S11 input matching below −10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.

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Acknowledgments

This work was supported in part by the National Science and Technology Major Projects of China under Grant 2012ZX03004007 and in part by the National Natural Science Foundation of China under Grant 61020106006, 61076029, 61222405, JCYJ20120616142625998.

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Authors and Affiliations

  1. Tsinghua National Laboratory for Information Science and Technology and Institute of Microelectronics, Tsinghua University, Beijing, 100084, China

    Xinwang Zhang, Baoyong Chi, Meng Cao, Ling Fu, Zhaokang Xia, Yun Yin, Hongxing Feng, Xing Zhang & Zhihua Wang

  2. School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR, 97331-5501, USA

    Patrick Chiang

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  1. Xinwang Zhang
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Correspondence to Xinwang Zhang.

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Zhang, X., Chi, B., Cao, M. et al. A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS. Analog Integr Circ Sig Process 77, 567–582 (2013). https://doi.org/10.1007/s10470-013-0168-x

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