A formal model for defining and classifying delay-insensitive circuits and systems Jan Tijmen Udding Original Articles Pages: 197 - 204
On the existence of delay-insensitive fair arbiters: Trace theory and its limitations David L. Black Original Articles Pages: 205 - 225
Compiling communicating processes into delay-insensitive VLSI circuits Alain J. Martin Original Articles Pages: 226 - 234
Semantics of digital networks containing indeterminate modules Robert M. KellerPrakash Panangaden Original Articles Pages: 235 - 245
Mapping image processing operations onto a linear systolic machine H. T. KungJon A. Webb Original Articles Pages: 246 - 257