A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints K. MasselosK. DanckaertH. De Man OriginalPaper 01 November 2000 Pages: 291 - 317
A Low Power 8 x 8 Direct 2-D DCT Chip Design Hao-Chieh ChangJiun-Ying JiuLiang-Gee Chen OriginalPaper 01 November 2000 Pages: 319 - 332
Reconfigurable Filter Coprocessor Architecture for DSP Applications S. RamanathanS.K. NandyV. Visvanathan OriginalPaper 01 November 2000 Pages: 333 - 359
Constant Number Serial Pipeline Multipliers K.Z. PekmestziP. Kalivas OriginalPaper 01 November 2000 Pages: 361 - 368
A Hardware Architecture for the LZW Compression and Decompression Algorithms Based on Parallel Dictionaries Ming-Bo Lin OriginalPaper 01 November 2000 Pages: 369 - 381
Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming Vera P. BeharChristo A. KabakchievLyubka A. Doukovska OriginalPaper 01 November 2000 Pages: 383 - 396
A New Neuro-Fuzzy Classifier with Application to On-Line Face Detection and Recognition J.S. TaurC.W. Tao OriginalPaper 01 November 2000 Pages: 397 - 409