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A Low Power 8 x 8 Direct 2-D DCT Chip Design

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Abstract

This paper presents the design and implementation of a low power 8 × 8 2-D DCT chip based on a computation-effective algorithm. Computational complexity can be reduced by simplifying the direct 2-D algorithm. Thus, the low power consumption is achieved due to complexity reduction. Besides, the parallel distributed-arithmetic (DA) technique is used to realize constant multiplication due to the low-power consideration. Additionally, the 2 V-power supply is practiced in circuit implementation for now and future battery operated applications. By using the TSMC 0.6 μm single-poly double-metal technology, 133 mW power consumption at 100 MHz and the 133 MHz maximum operation speed are achieved by critical path simulation.

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References

  1. N. Ahmed, T. Natarajan, and K.R. Rao, “Discrete Cosine Transform,” IEEE Trans. Commu., vol. COM-23, 1974, pp. 90–93.

    MathSciNet  Google Scholar 

  2. ISO/IEC, “Digital Compression and Coding of Continuous-Tone Still Images,” Int. Standard DIS 10918.

  3. Didier Le Gall, “MPEG: A Video Compression Standard for Multimedia Applications,” Communications of the ACM, vol. 34, no.4, 1991, pp. 46–58.

    Article  MathSciNet  Google Scholar 

  4. ISO/IEC/JTC1/SC29/WG11. Draft CD 13818-2, Recommendation H.262, Committee Draft.

  5. CCITT Study Group XV, TD35, “Draft Review of Recommendation H.261 Video Codec for Audiovisual Services at p£64 kbits/s,” Image Communication, August 1990, pp. 221–239.

  6. “Video Coding for Narrow Telecommunication Channels at <64 kbits/s,” Draft ITU-T Recommendation H.263, July 1995.

  7. D. Slawecki and W. Li, “DCT/IDCT Processor Design for High Data Rate Image Coding,” IEEE Trans. Circuits Syst.Video Technol., vol. 2, 1992, pp. 135–146.

    Article  Google Scholar 

  8. S. Uramoto, Y. Inoue, A. Takabetake, J. Takeda, Y. Yamashita, H. Terane, and M. Yoshimoto, “A 100 MHz 2-D Discrete Cosine Transform Core Processor,” IEEE J. Solid-State Circuits, vol. 27, 1992, pp. 492–499.

    Article  Google Scholar 

  9. T. Miyazaki, T. Nishitani, M. Edahiro, I. Ono, and K. Mitsuhashi, “DCT/IDCT Processor for HDTV Developed with DSP Silicon Compiler,” J. VLSI Signal Processing, vol. 5, 1993, pp. 39–46.

    Article  Google Scholar 

  10. A. Madisetti and A.N. Willson, “A 100 MHz 2-D 8x8 DCT/IDCT Processor for HDTV Applications,” IEEE Trans. Circuits Syst. Video Technol., vol. 5, 1995, pp. 158–165.

    Article  Google Scholar 

  11. SGS-THOMSON Microelectronics, “2-D Discrete Cosine Transform Image Processor,” Product No. IMSA121.

  12. T. Kuroda, T. Fujita, S. Mita, T. Nagamatsu, S. Yoshioka, K. Suzuki, F. Sano, M. Norishima, M. Murota, M. Kako, M. Kinugawa, M. Kakuma and T. Sakurai, “A 0.9 V, 150 MHz, 10 mV,4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme,” IEEE J. Solid-State Circuits, vol. 31, no.11, 1996, pp. 1770–1779.

    Article  Google Scholar 

  13. P. Duhamel and C. Guillemot, “Polynomial transform computation of 2-D DCT,” in Proc. ICASSP'90, April 1990, pp. 1515–1518.

  14. M. Vetterli, “Fast 2-D Discrete Cosine Transform,” in Proc. ICASSP'85, March 1995.

  15. N.I. Cho and S.U. Lee, “Fast Algorithm and Implementation of 2-D Discrete Cosine Transform,” IEEE Trans. Circuits Syst., vol. CAS-38, 1991, pp. 297–305.

    Google Scholar 

  16. N.I. Cho, I.Y. Dong, and S.U. Lee, “On the Regular Structure for the Fast 2-D DCT Algorithm,” IEEE Trans. Circuits Syst.-II, vol. CAS-40, 1993, pp. 259–266.

    Article  Google Scholar 

  17. V. Srinvasan and K.J.R. Liu, “VLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Application,” IEEE Trans. Circuits Syst. Video Technol., vol. 6, 1996, pp. 87–96.

    Article  Google Scholar 

  18. Y.P. Lee, T.H. Chen, M.J. Chen, and C.W. Ku, “A Cost-Effective Architecture for 8£8 2-DDCT/IDCT Using Direct Method,” IEEE Trans. Circuits Syst. Video Technol., vol 7. no3, 1997, pp. 459–467.

    Article  Google Scholar 

  19. J.H. Hsiao, L.G. Chen, T.D. Chiueh, and C.T. Chen, “High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine Transform,” IEEE Trans. Circuit Syst. Video Technol., vol. 5, 1995, pp. 218–224.

    Article  Google Scholar 

  20. S.A. White, “Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review,” IEEE ASSP Magazine, vol. 6, no.3, 1989, pp. 4–19.

    Article  Google Scholar 

  21. J.M. Rabaey, Digital Integrated Circuits–A Design Perspective, Upper Saddle River, NJ: Prentice Hall. International Editions, 1995.

    Google Scholar 

  22. N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design–Systems Perspective, 2nd edn., Reading, MA: Addison Wesley, 1993.

    Google Scholar 

  23. J. Yuan and C. Svensson, “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 23, no.1, 1989, pp. 2–70.

    Google Scholar 

  24. C. Nagendra, M.J. Irwin, and R.M. Owens, “Area-Time-Power Tradeoffs in Parallel Adders,” IEEE Trans. Circuits Syst.-II, vol. 43, no.10, 1996, pp. 689–702.

    Article  Google Scholar 

  25. J. Hunter and J.V. McCanny, “Discrete Consine Transform Generator for VLSI Synthesis,” in Proc. of IEEE Int. Conf. Acoustics, Speech, Signal Processing, Seattle, May 1998.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C, 10764

    Hao-Chieh Chang, Jiun-Ying Jiu, Li-Lin Chen & Liang-Gee Chen

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  1. Hao-Chieh Chang
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  2. Jiun-Ying Jiu
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  3. Li-Lin Chen
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  4. Liang-Gee Chen
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Chang, HC., Jiu, JY., Chen, LL. et al. A Low Power 8 x 8 Direct 2-D DCT Chip Design. The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology 26, 319–332 (2000). https://doi.org/10.1023/A:1026503416812

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