Guest editors' introduction Vojin G. OklobdzijaBelle Wei EditorialNotes 01 December 1996 Pages: 239 - 240
An efficient tree architecture for modulo 2 n +1 multiplication Zhongde WangG. A. JullienW. C. Miller OriginalPaper 01 December 1996 Pages: 241 - 248
δ-Bit serial binary addition with linear threshold networks Sorin CotofanaStamatis Vassiliadis OriginalPaper 01 December 1996 Pages: 249 - 264
Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding Chris DickFred Harris OriginalPaper 01 December 1996 Pages: 265 - 282
On recoding in arithmetic algorithms Miloš D. ErcegovacTomás Lang OriginalPaper 01 December 1996 Pages: 283 - 294
A new design for a lookahead carry generator Hercule KwanRobert Leonard Nelson Jr.Earl E. Swartzlander Jr. OriginalPaper 01 December 1996 Pages: 295 - 302
Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters Richard H. StrandbergLuis G. BustamanteJean-Claude Le Duc OriginalPaper 01 December 1996 Pages: 303 - 309
A 32-bit logarithmic number system processor Sheng-Chieh HuangLiang-Gee ChenThou-Ho Chen OriginalPaper 01 December 1996 Pages: 311 - 319
Design strategies for optimal hybrid final adders in a parallel multiplier Paul F. StellingVojin G. Oklobdzija OriginalPaper 01 December 1996 Pages: 321 - 331