A 32-bit logarithmic number system processor

  • Sheng-Chieh Huang
  • Liang-Gee Chen
  • Thou-Ho Chen


To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The basic concept behind DP is that variablex can be divided into two parts in bit representation to be implemented. Thus, ROM or PLA table can be reduced to a reasonable size and this will make a high precision design allowable. The basic idea of IDLA is that the function 20.x can be obtained approximately through iterative linear approximations. By this method, only adder, shifter and a small PLA are required, unlike the previous designs which require ROM and multiplier. The experiment results reveal that the proposed design is more attractive than the previous researches in the LNS processor.


Paper Award Permissible Error Linear Equivalent Method Logarithmic Number Logarithmic Number System 
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  1. 1.
    J.H. Lang, C.A. Zukowski, R.O. Lamaire, and C.H. An, “Integrated-circuit logarithmic arithmetic units”,IEEE Trans. Comput., Vol. C 34, pp. 475–483, May 1985.CrossRefGoogle Scholar
  2. 2.
    F.J. Taylor, R. Gill, J. Joseph, and J. Radke, “A 20-bit logarithmic number system processor”,IEEE Trans. Comput., Vol. 37, pp. 190–200, Feb. 1988.CrossRefGoogle Scholar
  3. 3.
    L.K. Yu and D.M. Lewis, “A 30-b integrated logarithmic number system processor”,IEEE J. Solid-State Circuits, Vol. 26, pp. 1433–1440, Oct. 1991.CrossRefGoogle Scholar
  4. 4.
    F.S. Lai, “The architecture and analysis of a hybrid number system processor”,IEEE Sym. on Circuit and System, pp. 803–806, 1992.Google Scholar
  5. 5.
    D.M. Lewis and L.K. Yu, “Algorithm design for a 30-bit integrated logarithmic processor”,IEEE Proc. 9th Symp. Comput. Arithmetic, pp. 192–199, 1989.Google Scholar
  6. 6.
    H. Henkel, “Improved addition for logarithmic number system”,IEEE Trans. Acoust. Speech, Signal Processing, Vol. 37, pp. 301–303, Feb. 1989.CrossRefGoogle Scholar
  7. 7.
    H.Y. Lo and J.L. Chen, “A hardwired generalized algorithm for generating the logarithm base-k by iteration”,IEEE Trans. Comput., Vol. C 36, pp. 1363–1367, Nov. 1987.CrossRefGoogle Scholar
  8. 8.
    S.C. Huang, L.G. Chen, and T.H. Chen, “The chip design of a 32-b logarithmic number system”,IEEE Sym. on Circuit and System, Vol. 4, pp. 167–170, 1994.Google Scholar
  9. 9.
    W.E. Ferguson, Jr. and T. Brightman, “Accurate and monotone approximations of some transcendental functions”,IEEE Proc. 10th Symp. Comput. Arithmetic, pp. 237–244, 1991.Google Scholar
  10. 10.
    D.M. Lewis, “Interlaeved memory function interpolators with application to an accurate LNS arithmetic unit”,IEEE Trans. Comput., Vol. 43, No. 8, pp. 974–982, Aug. 1994.CrossRefMATHGoogle Scholar
  11. 11.
    F.S. Lai and C.F.E. Wu “A hybrid number system processor with geometric and complex arithmetic capabilities”,IEEE Trans. Comput., Vol. 40, pp. 952–962, Aug. 1991.CrossRefGoogle Scholar

Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Sheng-Chieh Huang
    • 1
  • Liang-Gee Chen
    • 1
  • Thou-Ho Chen
    • 2
  1. 1.Department of Electrical EngineeringNational Taiwan UniversityTaipeiTaiwan R.O.C.
  2. 2.Department of Electronic EngineeringNan-Tai Institute of TechnologyTainanTaiwan R.O.C.

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