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A 32-bit logarithmic number system processor

  • Sheng-Chieh Huang
  • Liang-Gee Chen
  • Thou-Ho Chen
Article

Abstract

To design a 32-bit logarithmic number system (LNS) processor, this paper presents two novel techniques: Digit-Partition (DP) to design log2(1.x) function and Iterative Difference by Linear Approximation (IDLA) to design 20.x function. The basic concept behind DP is that variablex can be divided into two parts in bit representation to be implemented. Thus, ROM or PLA table can be reduced to a reasonable size and this will make a high precision design allowable. The basic idea of IDLA is that the function 20.x can be obtained approximately through iterative linear approximations. By this method, only adder, shifter and a small PLA are required, unlike the previous designs which require ROM and multiplier. The experiment results reveal that the proposed design is more attractive than the previous researches in the LNS processor.

Keywords

Paper Award Permissible Error Linear Equivalent Method Logarithmic Number Logarithmic Number System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Kluwer Academic Publishers 1996

Authors and Affiliations

  • Sheng-Chieh Huang
    • 1
  • Liang-Gee Chen
    • 1
  • Thou-Ho Chen
    • 2
  1. 1.Department of Electrical EngineeringNational Taiwan UniversityTaipeiTaiwan R.O.C.
  2. 2.Department of Electronic EngineeringNan-Tai Institute of TechnologyTainanTaiwan R.O.C.

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