Bit-Level systolic architectures for high performance IIR filtering S. C. KnowlesJ. G. McWhirterJ. V. McCanny OriginalPaper 01 August 1989 Pages: 9 - 24
Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP Takao NishitaniIchiro TamitaniKoichi Kikuchi OriginalPaper 01 August 1989 Pages: 25 - 34
A million transistor systolic array graphics engine Nader GharachorlooSatish GuptaChristos Zoulas OriginalPaper 01 August 1989 Pages: 35 - 43
Parallel implementation of synthetic aperture radar algorithms K. Wojtek PrzytulaJ. Greg Nash OriginalPaper 01 August 1989 Pages: 45 - 56
Cellular array processor CAP and applications Mitsuo IshiiHiroyuki SatoHiroaki Ishihata OriginalPaper 01 August 1989 Pages: 57 - 67
ASP modules: cost-effective building-blocks for real-time DSP systems R. M. Lea OriginalPaper 01 August 1989 Pages: 69 - 84