A tale of two designs: the cheapest and the most economic Vishwani D. Agrawal OriginalPaper Pages: 131 - 135
Test strategy planning using economic analysis I. D. DearC. D. DislisJ. Dick OriginalPaper Pages: 137 - 155
Economics of “design for test” to remain competitive in the 90s Farzad Zarrinfar OriginalPaper Pages: 171 - 177
The economics of scan-path design for testability Prab VarmaTushar Gheewala OriginalPaper Pages: 179 - 193
High Level Test Economics Advisor (Hi-TEA) Magdy AbadirAshish ParikhCynthia Murphy OriginalPaper Pages: 195 - 206
Multichip systems trade-off analysis tool Peter A. SandbornRajarshi GhoshAshish Parikh OriginalPaper Pages: 207 - 218
Trade-off analysis on cost and manufacturing technology of an electronic product: Case study Shekar RaoBert HaskellIan Yee OriginalPaper Pages: 219 - 228
Cost based surface mount PCB design evaluation M. AlexanderK. SríhariC. R. Emerson OriginalPaper Pages: 229 - 238
Sensitivity analysis in economics based test strategy planning J. H. DickE. TrischlerA. P. Ambler OriginalPaper Pages: 239 - 251
Boundary scan in board manufacturing Thomas A. ZiajaEarl E. Swartzlander Jr. OriginalPaper Pages: 263 - 268
Comparing quality assurance methods and the resulting design strategies: Experiences from complex designs C. v. Reventlow OriginalPaper Pages: 269 - 272
Trade-offs in scan path and BIST implementations for RAMs M. NicolaidisO. KebichiV. Castro Alves OriginalPaper Pages: 273 - 283
Techniques for estimating test length under random test Amitava MajumdarSarma B. K. Vrudhula OriginalPaper Pages: 285 - 297
Fuzzy optimization models for analog test decisions Mounir FaresBozena Kaminska OriginalPaper Pages: 299 - 305
Self-test of sequential circuits with deterministic test pattern sequences Arno KunzmannFrank Boehland OriginalPaper Pages: 307 - 312