1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes Pages: 127 - 127

2. Introduction

   • Magdy Abadir
   • Tony Ambler

   EditorialNotes Pages: 129 - 130

3. A tale of two designs: the cheapest and the most economic

   • Vishwani D. Agrawal

   OriginalPaper Pages: 131 - 135

4. Test strategy planning using economic analysis

   • I. D. Dear
   • C. D. Dislis
   • J. Dick

   OriginalPaper Pages: 137 - 155

5. Economic modeling of board test strategies

   • Brendan Davis

   OriginalPaper Pages: 157 - 169

6. Economics of “design for test” to remain competitive in the 90s

   • Farzad Zarrinfar

   OriginalPaper Pages: 171 - 177

7. The economics of scan-path design for testability

   • Prab Varma
   • Tushar Gheewala

   OriginalPaper Pages: 179 - 193

8. High Level Test Economics Advisor (Hi-TEA)

   • Magdy Abadir
   • Ashish Parikh
   • Cynthia Murphy

   OriginalPaper Pages: 195 - 206

9. Multichip systems trade-off analysis tool

   • Peter A. Sandborn
   • Rajarshi Ghosh
   • Ashish Parikh

   OriginalPaper Pages: 207 - 218

10. Trade-off analysis on cost and manufacturing technology of an electronic product: Case study

    • Shekar Rao
    • Bert Haskell
    • Ian Yee

    OriginalPaper Pages: 219 - 228

11. Cost based surface mount PCB design evaluation

    • M. Alexander
    • K. Sríhari
    • C. R. Emerson

    OriginalPaper Pages: 229 - 238

12. Sensitivity analysis in economics based test strategy planning

    • J. H. Dick
    • E. Trischler
    • A. P. Ambler

    OriginalPaper Pages: 239 - 251

13. Improving quality: Yield versus test coverage

    • Steven D. Millman

    OriginalPaper Pages: 253 - 261

14. Boundary scan in board manufacturing

    • Thomas A. Ziaja
    • Earl E. Swartzlander Jr.

    OriginalPaper Pages: 263 - 268

15. Comparing quality assurance methods and the resulting design strategies: Experiences from complex designs

    • C. v. Reventlow

    OriginalPaper Pages: 269 - 272

16. Trade-offs in scan path and BIST implementations for RAMs

    • M. Nicolaidis
    • O. Kebichi
    • V. Castro Alves

    OriginalPaper Pages: 273 - 283

17. Techniques for estimating test length under random test

    • Amitava Majumdar
    • Sarma B. K. Vrudhula

    OriginalPaper Pages: 285 - 297

18. Fuzzy optimization models for analog test decisions

    • Mounir Fares
    • Bozena Kaminska

    OriginalPaper Pages: 299 - 305

19. Self-test of sequential circuits with deterministic test pattern sequences

    • Arno Kunzmann
    • Frank Boehland

    OriginalPaper Pages: 307 - 312