A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and AC Circuits Michał TadeusiewiczStanisław Hałgas OriginalPaper Open access 06 March 2017 Pages: 147 - 156
A Parallel Test Application Method towards Power Reduction Ding DengYang GuoZhentao Li OriginalPaper 25 March 2017 Pages: 157 - 169
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling Vijay SheshadriVishwani D. AgrawalPrathima Agrawal OriginalPaper 15 March 2017 Pages: 171 - 187
Reliability Model for Multiple-Error Protected Static Memories Hadi Jahanirad OriginalPaper 28 February 2017 Pages: 189 - 207
Link Testing: a Survey of Current Trends in Network on Chip Babak AghaeiAhmad KhademzadehKambiz Badie OriginalPaper 10 March 2017 Pages: 209 - 225
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks Biswajit BhowmikJatindra Kumar DekaSantosh Biswas OriginalPaper 03 April 2017 Pages: 227 - 254
Total Ionizing Dose Effect and Single Event Burnout of VDMOS with Different Inter Layer Dielectric and Passivation Jiongjiong MoHua ChenFaxin Yu OriginalPaper 13 February 2017 Pages: 255 - 259
A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator Zhe LiuXiao-Peng YuWen-Quan Sui OriginalPaper 28 March 2017 Pages: 261 - 266
VI-Based Measurement System Focusing on Space Applications L. E. SeixasS. FincoS. P. Gimenez OriginalPaper 07 March 2017 Pages: 267 - 274