1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 21 March 2017 Pages: 141 - 141

2. Test Technology Newsletter

   News 28 February 2017 Pages: 143 - 145

   

3. A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and AC Circuits

   • Michał Tadeusiewicz
   • Stanisław Hałgas

   OriginalPaper Open access 06 March 2017 Pages: 147 - 156

   

4. A Parallel Test Application Method towards Power Reduction

   • Ding Deng
   • Yang Guo
   • Zhentao Li

   OriginalPaper 25 March 2017 Pages: 157 - 169

   

5. Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling

   • Vijay Sheshadri
   • Vishwani D. Agrawal
   • Prathima Agrawal

   OriginalPaper 15 March 2017 Pages: 171 - 187

   

6. Reliability Model for Multiple-Error Protected Static Memories

   • Hadi Jahanirad

   OriginalPaper 28 February 2017 Pages: 189 - 207

   

7. Link Testing: a Survey of Current Trends in Network on Chip

   • Babak Aghaei
   • Ahmad Khademzadeh
   • Kambiz Badie

   OriginalPaper 10 March 2017 Pages: 209 - 225

   

8. A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks

   • Biswajit Bhowmik
   • Jatindra Kumar Deka
   • Santosh Biswas

   OriginalPaper 03 April 2017 Pages: 227 - 254

   

9. Total Ionizing Dose Effect and Single Event Burnout of VDMOS with Different Inter Layer Dielectric and Passivation

   • Jiongjiong Mo
   • Hua Chen
   • Faxin Yu

   OriginalPaper 13 February 2017 Pages: 255 - 259

   

10. A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator

    • Zhe Liu
    • Xiao-Peng Yu
    • Wen-Quan Sui

    OriginalPaper 28 March 2017 Pages: 261 - 266

    

11. VI-Based Measurement System Focusing on Space Applications

    • L. E. Seixas
    • S. Finco
    • S. P. Gimenez

    OriginalPaper 07 March 2017 Pages: 267 - 274