Volume 29, Issue 5

October 2013

Special Issue on Verification and Testing Challenges in Future Microprocessor and SoC Designs

Issue Editors:

10 articles in this issue

Editorial
Vishwani D. Agrawal
EditorialNotes 15 October 2013 Pages: 617 - 617
Test Technology Newsletter

News 06 October 2013 Pages: 619 - 620
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs
Sandip Ray
Jay Bhadra
Li-C Wang
EditorialNotes 10 October 2013 Pages: 621 - 623
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
Lung-Jen Lee
OriginalPaper 13 September 2013 Pages: 625 - 634
LLVMVF: A Generic Approach for Verification of Multicore Software
Marcelo Sousa
Alper Sen
OriginalPaper 07 September 2013 Pages: 635 - 646
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Nicola Bombieri
Emad Ebeid
Michele Lora
OriginalPaper 22 October 2013 Pages: 647 - 667
Automatic Generation of System Level Assertions from Transaction Level Models
Lingyi Liu
Shobha Vasudevan
OriginalPaper 17 September 2013 Pages: 669 - 684
A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs
Yanyan Gao
Xi Li
OriginalPaper 02 October 2013 Pages: 685 - 695
A Novel Formalism for Partially Defined Asynchronous Feedback Digital Circuits
Gürkan Uygur
Sebastian M. Sattler
OriginalPaper 19 October 2013 Pages: 697 - 714
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces
Kusum Lata
Subir K. Roy
OriginalPaper 02 October 2013 Pages: 715 - 740

Navigation