1. Editorial

   • Vishwani D. Agrawal

   EditorialNotes 13 September 2011 Pages: 579 - 579

2. Test Technology Newsletter

   News 03 September 2011 Pages: 581 - 582

   

3. A New Design-for-Testability Method Based on Thru-Testability

   • Chia Yee Ooi
   • Hideo Fujiwara

   OriginalPaper 01 September 2011 Pages: 583 - 598

   

4. Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs

   • Brady Benware
   • Grzegorz Mrugalski
   • Jerzy Tyszer

   OriginalPaper Open access 26 August 2011 Pages: 599 - 609

   

5. Wavelet Neural Network Approach for Testing of Switched-Current Circuits

   • Guo Jierong
   • He Yigang
   • Liu Meirong

   OriginalPaper 03 September 2011 Pages: 611 - 625

   

6. Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions

   • Gilles Foucard
   • Paul Peronnard
   • Raoul Velazco

   OriginalPaper 10 September 2011 Pages: 627 - 633

   

7. Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers

   • Marcos Barcellos Hervé
   • Marcelo Moraes
   • Érika Cota

   OriginalPaper 03 September 2011 Pages: 635 - 646

   

8. A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect

   • Zhu Jianfeng
   • He Hu
   • Pan Liyang

   OriginalPaper 30 July 2011 Pages: 647 - 655

   

9. Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques

   • Debasis Mitra
   • Sarmishtha Ghoshal
   • Bhargab B. Bhattacharya

   OriginalPaper 13 August 2011 Pages: 657 - 671

   

10. Analog Circuit Fault Detection Using Location of Poles

    • Ashok Kavithamani
    • Venugopal Manikandan
    • Nanjundappan Devarajan

    Letter 11 August 2011 Pages: 673 - 678

    

11. Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect

    • Jianfeng Zhu
    • Hu He
    • Liyang Pan

    Erratum 06 September 2011 Pages: 679 - 679