A New Design-for-Testability Method Based on Thru-Testability Chia Yee OoiHideo Fujiwara OriginalPaper 01 September 2011 Pages: 583 - 598
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs Brady BenwareGrzegorz MrugalskiJerzy Tyszer OriginalPaper Open access 26 August 2011 Pages: 599 - 609
Wavelet Neural Network Approach for Testing of Switched-Current Circuits Guo JierongHe YigangLiu Meirong OriginalPaper 03 September 2011 Pages: 611 - 625
Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions Gilles FoucardPaul PeronnardRaoul Velazco OriginalPaper 10 September 2011 Pages: 627 - 633
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers Marcos Barcellos HervéMarcelo MoraesÉrika Cota OriginalPaper 03 September 2011 Pages: 635 - 646
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect Zhu JianfengHe HuPan Liyang OriginalPaper 30 July 2011 Pages: 647 - 655
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques Debasis MitraSarmishtha GhoshalBhargab B. Bhattacharya OriginalPaper 13 August 2011 Pages: 657 - 671
Analog Circuit Fault Detection Using Location of Poles Ashok KavithamaniVenugopal ManikandanNanjundappan Devarajan Letter 11 August 2011 Pages: 673 - 678
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect Jianfeng ZhuHu HeLiyang Pan Erratum 06 September 2011 Pages: 679 - 679