1. Editorial

   • Vishwani D. Agrawal

   Editorial Board Pages: 5 - 6

2. Test Technology Technical Council Newsletter

   • A. Ivanov

   Legacy Pages: 7 - 8

3. List of Reviewers

   Legacy Pages: 9 - 10

4. Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

   • S.J. Spinks
   • C.D. Chalk
   • M. Zwolinski

   OriginalPaper Pages: 11 - 23

5. Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks

   • V. Stopjaková
   • P. Malošek
   • M. Margala

   OriginalPaper Pages: 25 - 37

6. Control and Observation Structure for Analog Circuits with Current Test Data

   • Chun-Lung Hsu

   OriginalPaper Pages: 39 - 44

7. A Graph-Based Approach to Power-Constrained SOC Test Scheduling

   • Chih-Pin Su
   • Cheng-Wen Wu

   OriginalPaper Pages: 45 - 60

8. Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints

   • Valentin Mureşan
   • Xiaojun Wang
   • Mircea Vlăduţiu

   OriginalPaper Pages: 61 - 78

9. A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques

   • D. Appello
   • A. Fudoli
   • M. Sonza Reorda

   OriginalPaper Pages: 79 - 87

10. Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

    • Kanad Chakraborty

    OriginalPaper Pages: 89 - 108

11. Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

    • O. Novák
    • Z. Plíva
    • K. Gucwa

    OriginalPaper Pages: 109 - 122