1. Editorial

   • Vishwani D. Agrawal

   OriginalPaper Pages: 75 - 75

2. Guest Editorial

   • Niraj K. Jha

   OriginalPaper Pages: 77 - 77

3. Design for Testability Techniques at the Behavioral and Register-Transfer Levels

   • Sujit Dey
   • Anand Raghunathan
   • Kenneth D. Wagner

   OriginalPaper Pages: 79 - 91

4. High-Level Controllability and Observability Analysis for Test Synthesis

   • Frank F. Hsu
   • Janak H. Patel

   OriginalPaper Pages: 93 - 103

5. RTL Test Justification and Propagation Analysis for Modular Designs

   • Yiorgos Makris
   • Alex Orailogcaron;lu

   OriginalPaper Pages: 105 - 120

6. Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays

   • Li-C. Wang
   • Magdy S. Abadir

   OriginalPaper Pages: 121 - 135

7. Synthesis of Native Mode Self-Test Programs

   • Jian Shen
   • Jacob A. Abraham

   OriginalPaper Pages: 137 - 148

8. Allocation Techniques for Reducing BIST Area Overhead of Data Paths

   • Ishwar Parulkar
   • Sandeep K. Gupta
   • Melvin A. Breuer

   OriginalPaper Pages: 149 - 166

9. High-Level Test Synthesis for Behavioral and Structural Designs

   • Christos A. Papachristou
   • Mikhail Baklashov
   • Kowen Lai

   OriginalPaper Pages: 167 - 188

10. Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures

    • Nilanjan Mukherjee
    • Ramesh Karri

    OriginalPaper Pages: 189 - 200

11. Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

    • Srivaths Ravi
    • Indradeep Ghosh
    • Sujit Dey

    OriginalPaper Pages: 201 - 212