An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture C. AktoufC. RobachG. Mazare OriginalPaper Pages: 171 - 185
The Design and Implementation of an On-Line Testable UART J. YeandelD. ThulbornS. Jones OriginalPaper Pages: 187 - 198
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems M.F. AbdullaC.P. RavikumarAnshul Kumar OriginalPaper Pages: 199 - 216
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation Zohair SahraouiFrancky CatthoorHugo de Man OriginalPaper Pages: 217 - 238
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits Lakshminarayana PappuMichael L. BushnellSrinivas Mandyam-Komar OriginalPaper Pages: 239 - 254
Combinatorial Analysis of Check Set Construction for Algorithm-Based Fault Tolerance Systems De-Qiang WangLian-Chang Zhao OriginalPaper Pages: 255 - 260