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Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET

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Abstract

In this article, we investigated the influence of non-identical interface trap charges (ITCs) (positive or donor and negative or acceptor) on the behavior of ferroelectric gate oxide tunnel field-effect transistor (Ferro-TFET) concerning various electrical parameters such as DC, analog/RF, and linearity distortion parameters. The conventional Ferro-TFET is optimized for reducing ambipolarity and improving on-current through source-gate overlap and gate-drain underlap. The optimized structure is considered for 5 nm gate overlap to source and 20 nm gate underlap to drain. Sentaurus TCAD device simulator is used to investigate distinct behavior metrics like transfer characteristics, Cgd, Cgs, Cgg,cut-off frequency (fT), and gain-bandwidth product (GBP) for the presence of a different distribution of ITCs (uniform and Gaussian trap distribution) on the optimized Ferro-TFET structure. Further to scrutinize the influence of ITCs on linearity behavior of Ferro-TFET, the variables such as gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point are analyzed. In this study, the Ferro-TFET with ITCs at gate oxide/ channel interface shows better immunity in terms of various performance metrics in contrast to the conventional TFET structures. Therefore, this Ferro-TFET is explored for analog, and RF applications as it shows superior performance.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, GIMT Guwahati, Guwahati, Assam, India, 781017

    Basab Das

  2. Department of Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India, 788010

    Brinda Bhowmick

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  1. Basab Das
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Concept, Manuscript writing – Basab Das.

Review and editing- Dr. Brinda Bhowmick.

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Correspondence to Basab Das.

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Das, B., Bhowmick, B. Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET. Silicon 15, 2359–2369 (2023). https://doi.org/10.1007/s12633-022-02167-8

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