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Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective

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Abstract

This paper extensively studies the spacer technology, including low-k/high-k, single/dual dielectrics on the device performances focusing on the leakage current. The tactical use of a spacer, introduction of a low bandgap material as a pocket on the source side along with the incorporation of gate dielectrics helped in improving the switching ratio effectively. A systematic comparison is made in between the conventional symmetrical single low-k spacer 3D FinFET and the proposed optimized 3D FinFET. Various device architectures are evaluated by showing significant improvements in on current (Ion) and off state leakage (Ioff), leading to a high switching ratio (Ion/Ioff) and the subthreshold slope (SS). An Ion/Ioff of value 1 × 106 indicates sufficient electrostatics to control over the channel, and our study results in ~8 time of this value. These parameters are obtained after the appropriate selection of low-k & high-k spacer length on both sides of the source and drain. The use of SiGe material near the source side to modulate carrier mobility and incorporating high-k gate dielectric to suppress leakage.

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Authors and Affiliations

  1. School of Electronics Engineering, KIIT University, Bhubaneswar, Odisha, India

    Asharani Samal & Sushanta Kumar Mohapatra

  2. Department of Electronics & Communication, Indian Institute of Information Technology Design and Manufacturing (IIITDM), Chennai, Kancheepuram, India

    Kumar Prasannajit Pradhan

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  1. Asharani Samal
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  2. Kumar Prasannajit Pradhan
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  3. Sushanta Kumar Mohapatra
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Correspondence to Kumar Prasannajit Pradhan.

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Samal, A., Pradhan, K.P. & Mohapatra, S.K. Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective. Silicon 13, 2655–2660 (2021). https://doi.org/10.1007/s12633-020-00618-8

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  • DOI: https://doi.org/10.1007/s12633-020-00618-8

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