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Effect of the Single- and Dual-k Spacers on a Negative-capacitance Fin Field-effect Transistor

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Abstract

The influence of single- and double-k spacer structures on the performance of a negative-capacitance fin field-effect transistor (NC-FinFET) is investigated in this work. Sentaurus technology computer-aided design simulation reveals that due to the negative- capacitance effect, the difference between the single-k and double-k spacers on the FinFET performance is reflected in the drain-induced barrier lowing (DIBL), subthreshold swing (SS), and switching current ratio. The double-k spacer shows stronger gate controllability and better capacitance matching than the single-k spacer. Thus, the double-k spacer is more beneficial to improving intrinsic delay than the single-k spacer. In addition, by adjusting the combination of spacer materials and structures, the NC-FinFET can achieve a switching current ratio of up to 108, an SS of 57 mV/dec, and a DIBL of − 47 mV/V. This work provides spacer optimizations via selecting appropriate structure and materials for NC-FinFET.

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References

  1. Kim S, Lee K, Lee JH et al (2020) Vertically stacked gate-all-around structured tunneling-based ternary-CMOS. IEEE Trans Electron Devices 67:3889–3893

    Article  CAS  Google Scholar 

  2. Herrera F, Hirano Y, Miura-Mattausch M et al (2019) Advanced Short-channel-effect modeling with applicability to device optimization—Potentials and scaling. IEEE Trans Electron Devices 66:3726–3733

    Article  CAS  Google Scholar 

  3. Narendar V, Narware P, Bheemudu V et al (2020) Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET. Silicon 12:2283–2291

    Article  CAS  Google Scholar 

  4. Arulananth TS, Prasad SVS, Rao KS (2021) High-k materials in multi-gate FET devices, 1st edn. CRC Press, Boca Raton

    Google Scholar 

  5. Li KS, Chen PG, Lai TY et al (2015) Sub-60mV-swing negative-capacitance FinFET without hysteresis. In: 2015 IEEE International Electron Devices Meeting (IEDM), pp 22 – 6

  6. Zhou J, Han G, Li Q et al (2016) Ferroelectric HfZrO x Ge and GeSn PMOSFETs with Sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved I ds. In: 2016 IEEE International Electron Devices Meeting (IEDM), pp 12 – 2

  7. Krivokapic Z, Rana U, Galatage R et al (2017) December) 14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications. In: 2017 IEEE International Electron Devices Meeting (IEDM), pp 15 – 1

  8. Chung W, Si M, Peide DY (2017), December Hysteresis-free negative capacitance germanium CMOS FinFETs with Bi-directional Sub-60 mV/dec. In: 2017 IEEE International Electron Devices Meeting (IEDM), pp 15 – 3

  9. Zhou J, Wu J, Han G et al (2017), December Frequency dependence of performance in Ge negative capacitance PFETs achieving sub-30 mV/decade swing and 110 mV hysteresis at MHz. In: 2017 IEEE International Electron Devices Meeting (IEDM), pp 15 – 5

  10. Yu T, Lü W, Zhao Z et al (2021) Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors. Microelectron J 108:104981

    Article  CAS  Google Scholar 

  11. Lin YK, Agarwal H, Kao MY et al (2019) Spacer engineering in negative capacitance FinFETs. IEEE Electron Device Lett 40:1009–1012

    Article  CAS  Google Scholar 

  12. Sreenivasulu VB, Narendar V (2021) Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length. AEU-Int J Electron Commun 137:153803

    Article  Google Scholar 

  13. Sachid AB, Chen MC, Hu C (2016) FinFET With High-κ Spacers for Improved Drive Current. IEEE Electron Device Lett 37:835–838

    Article  CAS  Google Scholar 

  14. Lin CC, Wu YJ, You WX, Su P (2020) Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers. In: International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp 62–63

  15. Ko H, Kim J, Kang M et al (2017) Investigation and analysis of dual-k spacer with different materials and spacer lengths for nanowire-FET performance. Solid-State Electron 136:68–74

    Article  CAS  Google Scholar 

  16. Mohanty SS, Mishra S, Mohapatra M, Mishra GP (2020) July). High Speed Buried Channel In 0.53 Ga 0.47 As/InP MOSFET with Corner Spacer for Low Power Applications. IEEE VLSI Device Circuit and System. VLSI DCS), pp 210–213

  17. Amrouch H, Pahwa G, Gaidhane AD et al (2018) Negative capacitance transistor to address the fundamental limitations in technology scaling: Processor performance. IEEE Access 6:52754–52765

    Article  Google Scholar 

  18. Lin CI, Khan AI, Salahuddin S et al (2016) Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans Electron Devices 63:2197–2199

    Article  Google Scholar 

  19. Agarwal H, Kushwaha P, Duarte JP et al (2018) Engineering negative differential resistance in NCFETs for analog applications. IEEE Trans Electron Devices 65(5):2033–2039

    Article  CAS  Google Scholar 

  20. Zhao Z, Yu T, Si P et al (2020) Superior performance of a negative-capacitance double-gate Junctionless field-effect transistor with additional source-drain doping. Inf Midem-J Microelectron Electron Compon Mater 50:169–178

    Google Scholar 

  21. Kaushal S, Kaundal S, Rana AK (2021) Impact of spacer configuration on negative capacitance multi gate Junctionless FET. In: International Conference on Computer Communication and Informatics (ICCCI), pp 1–5

  22. Swain SK, Das SK, Biswal SM et al (2019) Effect of high-K spacer on the performance of non-uniformly doped DG-MOSFET. In: Devices for Integrated Circuit (DevIC), pp 510–514

  23. Gupta N, Kumar A (2021) Numerical assessment of high-k spacer on symmetric S/D underlap GAA junctionless accumulation mode silicon nanowire MOSFET for RFIC design. Appl Phys A-Mater Sci Process 127:1–8

    Article  Google Scholar 

  24. Sharma R, Rathore RS, Rana AK (2018) Impact of High-k spacer on device performance of nanoscale underlap fully depleted SOI MOSFET. J Circuits Syst Comput 27:1850063

    Article  Google Scholar 

  25. Sreenivasulu VB, Narendar V (2021) A comprehensive analysis of junctionless tri-gate (TG) FinFET towards low-power and high-frequency applications at 5-nm gate length. Silicon. https://doi.org/10.1007/s12633-021-00987-8

  26. Zhou H, Kwon D, Sachid AB et al (2018) Negative capacitance, n-channel, Si FinFETs: Bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect. In: IEEE Symposium on VLSI Technology, pp 53–54

  27. Yao Y, Sun Y, Li X et al (2020) Novel reconfigurable field-effect transistor with asymmetric spacer engineering at drain side. IEEE Trans Electron Devices 67:751–757

    Article  CAS  Google Scholar 

  28. Zhou J, Han G, Li J et al (2018) Negative differential resistance in negative capacitance FETs. IEEE Electron Device Lett 39(4):622–625

    Article  CAS  Google Scholar 

  29. Si P, Zhang K, Yu T et al (2020) Analog/RF performance analysis of nanometer negative capacitance FDSOI transistors. Inf Midem-J Microelectron Electron Compon Mater 50:47–54

    Google Scholar 

  30. Sreenivasulu VB, Narendar V (2021) Design insights into RF/analog and linearity/distortion of spacer engineered multi-fin SOI FET for terahertz applications. Int J RF Microw Comput-Aid Eng 31:e22875

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Acknowledgements

This work is supported by Zhejiang Provincial Natural Science Foundation of China (grant LY22F040001), and the National Natural Science Foundation of China (grant 62071160).

Funding

This work is supported by the National Natural Science Foundation of China (grant 62071160), and Zhejiang Provincial Natural Science Foundation of China (grant LY22F040005).

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Authors and Affiliations

  1. Key Laboratory for RF Circuits and Systems, Hangzhou Dianzi University, Ministry of Education, Hangzhou, China

    Mengxue Guo, Weifeng Lü, Mengjie Zhao & Ziqiang Xie

Authors
  1. Mengxue Guo
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  2. Weifeng Lü
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  3. Mengjie Zhao
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  4. Ziqiang Xie
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Contributions

Mengxue Guo developed the idea, performed the device design, and wrote the original draft. Weifeng Lü supervised the process of this work as well as revised the draft. Mengjie Zhao carried out the experiment. Ziqiang Xie reviewed the draft. All authors approved the final manuscript.

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Correspondence to Weifeng Lü.

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Guo, M., Lü, W., Zhao, M. et al. Effect of the Single- and Dual-k Spacers on a Negative-capacitance Fin Field-effect Transistor. Silicon 14, 10827–10835 (2022). https://doi.org/10.1007/s12633-022-01805-5

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