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Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation

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Abstract

An improved subthreshold analytical model of Dual Material Double Gate Junctionless Tunnel FET (DMDG JLTFET) with stacked / hetero-dielectric gate oxide structure is proposed. The stacked gate oxide structure comprises of Silicon-dioxide (SiO2) and Titanium Oxide (TiO2). The high-K gate stack engineered device overcomes the Short Channel Effects (SCEs) caused by the ultrathin silicon devices. The subthreshold analysis is carried out by solving a two-dimensional Poisson’s equation using Parabolic approximation method. These characteristics are analyzed against various device parameters. Also, the impact of different high-K gate oxide materials with SiO2 is also studied. A comparative analysis of short channel effects for DMDG TFET and DMDG JLTFET has been carried out. The results reveal that the proposed device provides better ION current, low leakage current and improved Transconductance-to-drain current ratio. Using TCAD Sentaurus device simulator, the subthreshold analytical model results have been simulated and verified with other TFET models.

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Authors and Affiliations

  1. Jerusalem College of Engineering, Chennai, 600100, India

    Lakshmi Priya G

  2. Thiagarajar College of Engineering, Madurai, 625015, India

    Balamurugan N B

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  1. Lakshmi Priya G
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  2. Balamurugan N B
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Correspondence to Lakshmi Priya G.

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G, L.P., N B, B. Improvement of Subthreshold Characteristics of Dopingless Tunnel FET Using Hetero Gate Dielectric Material: Analytical Modeling and Simulation. Silicon 12, 2189–2201 (2020). https://doi.org/10.1007/s12633-019-00314-2

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  • DOI: https://doi.org/10.1007/s12633-019-00314-2

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