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Device performance limit of monolayer SnSe2 MOSFET

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Abstract

Two-dimensional (2D) semiconductors are attractive channels to shrink the scale of field-effect transistors (FETs), and among which the anisotropic one is more advantageous for a higher on-state current (Ion). Monolayer (ML) SnSe2, as an abundant, economic, nontoxic, and stable two-dimensional material, possesses an anisotropic electronic nature. Herein, we study the device performances of the ML SnSe2 metal-oxide-semiconductor FETs (MOSFETs) and deduce their performance limit to an ultrashort gate length (Lg) and ultralow supply voltage (Vdd) by using the ab initio quantum transport simulation. An ultrahigh Ion of 5,660 and 3,145 µA/µm is acquired for the n-type 10-nm-Lg ML SnSe2 MOSFET at Vdd = 0.7 V for high-performance (HP) and low-power (LP) applications, respectively. Specifically, until Lg scales down to 2 and 3 nm, the MOSFETs (at Vdd = 0.65 V) surpass Ion, intrinsic delay time (τ), and power-delay product (PDP) of the International Roadmap for Device and Systems (IRDS, 2020 version) for HP and LP devices for the year 2028. Moreover, the 5-nm-Lg ML SnSe2 MOSFET (at Vdd = 0.4 V) fulfills the IRDS HP device and the 7-nm-Lg MOSFET (at Vdd = 0.55 V) fulfills the IRDS LP device for the year 2034.

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Acknowledgment

This work was supported by the Beijing Natural Science Foundation of China (No. 4212046), the National Natural Science Foundation of China (Nos. 11704008 and 91964101), the Support Plan of Yuyou Youth, and the fund of high-level characteristic research direction from North China University of Technology.

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Authors and Affiliations

  1. College of Mechanical and Material Engineering, North China University of Technology, Beijing, 100144, China

    Hong Li, Jiakun Liang, Qida Wang & Fengbin Liu

  2. Beijing Key Laboratory of Long-life Technology of Precise Rotation and Transmission Mechanisms, Beijing Institute of Control Engineering, Beijing, 100094, China

    Gang Zhou, Tao Qing & Shaohua Zhang

  3. State Key Laboratory of Mesoscopic Physics and Department of Physics, Peking University, Beijing, 100871, China

    Jing Lu

  4. Collaborative Innovation Center of Quantum Matter, Beijing, 100871, China

    Jing Lu

  5. Peking University Yangtze Delta Institute of Optoelectronics, Nantong, 226000, China

    Jing Lu

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  1. Hong Li
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  2. Jiakun Liang
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  3. Qida Wang
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  4. Fengbin Liu
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Correspondence to Hong Li or Jing Lu.

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Li, H., Liang, J., Wang, Q. et al. Device performance limit of monolayer SnSe2 MOSFET. Nano Res. 15, 2522–2530 (2022). https://doi.org/10.1007/s12274-021-3785-1

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