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Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm

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Abstract

This paper presents the result of experiments conducted in mesh networks on different routing algorithms, traffic generation schemes and switching schemes. A new network on chip (NoC) topology based on partial interconnection of mesh network is proposed and a routing algorithm supporting the proposed architecture is developed. The proposed architecture is similar to standard mesh networks, where four extra bidirectional channels are added which remove the congestion and hotspots compared to standard mesh networks with fewer channels. Significant improvement in delay (60% reduction) and throughput (60% increase) was observed using the proposed network and routing when compared with the ideal mesh networks. An increase in number of channels makes the switches expensive and could increase the area and power consumption. However, the proposed network can be useful in high speed applications with some compromise on area and power.

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Authors and Affiliations

  1. Indian Institute of Technology, Kanpur, 208016, India

    Sudhanshu Choudhary & Shafi Qureshi

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  1. Sudhanshu Choudhary
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  2. Shafi Qureshi
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Correspondence to Sudhanshu Choudhary.

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Sudhanshu Choudhary received bachelor degree in electronics and communication engineering from Birla Institute of Technology, MESRA Ranchi, India in 2002 and master degree from Indian Institute of Information Technology & Management Gwalior, India in 2006. He joined IIT Kanpur in 2006 as a Ph.D. candidate in the Department of Electrical Engineering at IIT Kanpur.

His research interests include microelectronics, very large scale integration (VLSI) testing and physical design.

Shafi Qureshi received Bachelor degree in electrical engineering from University of Kashmir, India in 1974 and Ph.D. degree from University of California, Berkeley, USA in 1991. He joined IIT Kanpur in 1992 and became professor in the Department of Electrical Engineering in 1997. He is senior member of IEEE and fellow of Institution of Electronics and Telecommunication Engineers (IETE) India.

His research interests include semiconductor device physics and modeling, thin film transistors, and VLSI design.

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Choudhary, S., Qureshi, S. Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm. Int. J. Autom. Comput. 9, 403–413 (2012). https://doi.org/10.1007/s11633-012-0661-1

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  • DOI: https://doi.org/10.1007/s11633-012-0661-1

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