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Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems

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Abstract

The advancement in wireless telecommunication technologies like 3G, 4G and now 5G enrich the demand of high performance portable devices, operating at high frequencies i.e. from few hundred MHz to several GHz. High performance can only be achieved at the cost of high power dissipation. Nowadays, the use of FPGAs is rapidly increasing due to its low cost and smaller time to market. Today’s high end FPGAs are capable of implementing high performance designs such as transceivers for RF application, signal processing and image processing applications etc. This is only possible due to their complex designs that includes on chip dedicated multipliers, Dual RAM blocks, Ethernet and DCMs etc. Since FPGAs consume large amount of power, it becomes a challenge for the designers to implement low power battery operated communication systems. Several power estimation models are available in literature for early stage power estimation of FPGAs in the synthesis design flow but they provide less accuracy (high percentage error) for the designs incorporated with low power reduction technique. This paper presents the limitation of existing power estimation model proposed by Deng. The given model is converted into a script using MATLAB. The power values estimated from the power model (script) are compared with the high level synthesis tool: Xpower Analyzer targeted to Virtex FPGA. For estimation of power values, an embedded multiplier is synthesized for two different configurations: one with ‘CE’ (low power) and another without ‘CE’ for different I/O vector length. The results suggested that the given low level power estimation models provide less accuracy (high % error) for the designs incorporated with low power reduction technique i.e. with ‘CE’. Further, there is a scope of remodel the existing model for the observed shortcoming.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Sector-62, Noida, Uttar Pradesh, India

    Gaurav Verma, Manish Kumar & Vijay Khare

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  1. Gaurav Verma
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  2. Manish Kumar
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  3. Vijay Khare
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Correspondence to Gaurav Verma.

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Verma, G., Kumar, M. & Khare, V. Low Power Synthesis and Validation of an Embedded Multiplier for FPGA Based Wireless Communication Systems. Wireless Pers Commun 95, 365–373 (2017). https://doi.org/10.1007/s11277-016-3897-1

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  • DOI: https://doi.org/10.1007/s11277-016-3897-1

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