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Low-cost and compact design method for reversible sequential circuits

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Abstract

Reversible logic plays an important role in nanotechnology-based systems; therefore, it has become an interesting topic for many researchers in this field. Although many researchers are investigating techniques to synthesize reversible combinational logic, few are working in the field of reversible sequential logic. The traditional method to design a sequential circuit is a replacement technique. In this technique, in order to design a reversible sequential circuit, all parts of an irreversible design (e.g., latches and flip-flops and associated combinational gates) are replaced by their reversible counter parts, which leads to circuits with high quantum cost. In this paper, we propose a direct and compact design of reversible synchronous sequential circuits. The EXOR of Products of EXOR (EPOE) expressions are applied, to reduce the quantum cost of sequential logic circuits. We present designs for some practical sequential circuits, such as state machines, counters and shift registers. To show the efficiency of the proposed method, we have designed a proof of concept of our designs to design a practical sequential system: a reversible self-controlled serial adder. Our designs considerably reduce performance cost factors: including quantum cost, number of constant inputs or the number of garbage outputs and delay.

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Authors and Affiliations

  1. Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran

    Zeinab Kalantari & Somayeh Jassbi

  2. Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran

    Mohammad Eshghi

  3. Department of Computer Engineering, Shahid Bahonar University of Kerman, Kerman, Iran

    Majid Mohammadi

Authors
  1. Zeinab Kalantari
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  2. Mohammad Eshghi
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  3. Majid Mohammadi
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  4. Somayeh Jassbi
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Correspondence to Mohammad Eshghi.

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Kalantari, Z., Eshghi, M., Mohammadi, M. et al. Low-cost and compact design method for reversible sequential circuits. J Supercomput 75, 7497–7519 (2019). https://doi.org/10.1007/s11227-019-02912-8

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  • DOI: https://doi.org/10.1007/s11227-019-02912-8

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