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Implementation of chaotic circuits with a digital time-delay block

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Abstract

In this paper, the implementation of time-delay chaotic circuits is investigated. To implement the time-delay block, a solution based on a digital circuitry has been adopted. This solution leads to a programmable hardware which can be realized by using available field programmable gate arrays. In this paper, issues raised from this implementation such as the behavior of the system with respect to the precision and the sampling rate of the conversion process have been investigated. The synchronization error is proposed as an indicator of the accuracy of the whole implementation.

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Authors and Affiliations

  1. Dipartimento di Ingegneria Elettrica Elettronica e Informatica, Universita degli Studi di Catania, Catania, Italy

    Viet-Thanh Pham, Luigi Fortuna & Mattia Frasca

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  1. Viet-Thanh Pham
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  2. Luigi Fortuna
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  3. Mattia Frasca
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Correspondence to Mattia Frasca.

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Pham, VT., Fortuna, L. & Frasca, M. Implementation of chaotic circuits with a digital time-delay block. Nonlinear Dyn 67, 345–355 (2012). https://doi.org/10.1007/s11071-011-9982-9

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  • DOI: https://doi.org/10.1007/s11071-011-9982-9

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