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A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials

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Abstract

The main motivation of this review is to study the evolution of first and second level of interconnect materials used in memory device semiconductor packaging. Evolutions of bonding wires from gold (Au) to silver (Ag) or copper (Cu) have been reported and studied in previous literatures for low-cost solution, but Au wire still gives highest rating in terms of the performance of temperature humidity test, high temperature storage, and bond-ability, etc. However, a new bonding wire material, Au-coated Ag, is recently developed to be an alternative solution which gives comparable performance, but lower cost compared to Au wire. In the first section of the article, the influence of a variety of factors were reviewed, which includes reliability performance and interfacial reaction that determines the performance of Au-coated Ag to reach for developing high reliability of bonded devices. With respect to second-level interconnects, SAC305 and SAC302 solder alloys give a balance performance between temperature cycling testing and drop testing, which are widely used in many field applications, such as mobile, consumer and computer. SAC405 and LF35 are developed for specific requirements such as SAC405 owns better temperature cycling performance, whereas LF35 gives excellent drop performance compared to SAC305 or SAC302. However, with market demands on automotive electronics get strong in recent years, solder joint reliability is being reviewed and discussed, especially in temperature cycling performance. Typical solder alloys on Ni/Au surface finish were not designed for automotive application to fulfill the requirement of board level reliability. Hence, newly developed solder alloys with Sn/Ag/Cu/Bi/Ni elements and Cu-OSP substrate surface finishes will be reviewed in the second section of the article.

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Acknowledgements

The authors would like to take this opportunity to thank support from Micron Memory Taiwan for the paper publication.

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Authors and Affiliations

  1. Micron Memory Taiwan Co. Ltd., Taichung City, 42152, Taiwan

    Yong Sheng Zou, Chong Leong Gan & Min-Hua Chung

  2. Micron Technology Inc., 110 Holger Way, San Jose, CA, 95134, USA

    Hem Takiar

  3. Houli District, No. 369, Sec 4, Sanfeng Road, Taichung City, 42151, Taiwan

    Yong Sheng Zou

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  1. Yong Sheng Zou
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Zou, Y.S., Gan, C.L., Chung, MH. et al. A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials. J Mater Sci: Mater Electron 32, 27133–27147 (2021). https://doi.org/10.1007/s10854-021-07105-9

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