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Logic Locking: A Survey of Proposed Methods and Evaluation Metrics

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Abstract

The outsourcing business model is dominating the semiconductor industry. Due to this loss of control over the design flow, several threats have become a major source of concern, including overproduction and IP overuse. For over a decade, several solutions have been proposed in the literature to counteract such threats. These solutions consist in hiding the behavior of the IPs/ICs until the design house securely unlocks them. This way, only unlocked IPs/ICs can be used properly while locked ones produce erroneous data. In this paper, we survey logic locking approaches and discuss locking quality in hiding expected behavior and in resisting to attacks.

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Funding

This work is funded by project MOOSIC ANR-18-CE39–0005 of the French National Research Agency (ANR).

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  1. LIRMM, Université de Montpellier, CNRS, 161 rue Ada, Montpellier, France

    Sophie Dupuis & Marie-Lise Flottes

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  1. Sophie Dupuis
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Correspondence to Sophie Dupuis.

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Dupuis, S., Flottes, ML. Logic Locking: A Survey of Proposed Methods and Evaluation Metrics. J Electron Test 35, 273–291 (2019). https://doi.org/10.1007/s10836-019-05800-4

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