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An Integrated on-Silicon Verification Method for FPGA Overlays

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Abstract

Field Programmable Gate Arrays (FPGAs) gain popularity as higher-level tools evolve to deliver the benefits of re-programmable silicon to engineers and scientists at all levels of expertise. In order to use FPGAs efficiently, new CAD tools and modern architectures are needed for the growing demands of heterogeneous computing paradigms. Overlay architectures have become a popular option to support a variety of high-performance computing applications implemented on heterogeneous computing platforms. However, most of these architectures cannot offer an efficient way to dynamically debug and repair them. In this paper, we propose a superimposed virtual coarse-grained reconfigurable architecture, embedded with on-demand debug and self-healing capabilities. The proposed method automatically creates flexible techniques for in-circuit error detection and correction of generic Processing Elements and Virtual Channels. The debugging infrastructure is integrated in the design with tailor-made CAD tools, making feasible to rapidly debug and repair virtual architectures with minimal use of additional FPGA resources.

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Acknowledgments

This work has been supported by the European Commission in the context of the European Union Horizon 2020 Framework Programme (H2020-EU.1.2.2.) under grant agreement number 671653.

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Authors and Affiliations

  1. ELIS Department, Computer Systems Lab, Ghent University, Ghent, B-9052, Belgium

    Alexandra Kourfali & Dirk Stroobandt

  2. Chair for Embedded Systems for Information Technology, Ruhr University of Bochum, Bochum, 44780, Germany

    Florian Fricke

  3. Chair for Computer Engineering, Technical University of Cottbus, Senftenberg, 01968, Germany

    Michael Huebner

Authors
  1. Alexandra Kourfali
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  2. Florian Fricke
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  3. Michael Huebner
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  4. Dirk Stroobandt
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Correspondence to Alexandra Kourfali.

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Responsible Editor: L. M. Bolzani Pöhls

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Kourfali, A., Fricke, F., Huebner, M. et al. An Integrated on-Silicon Verification Method for FPGA Overlays. J Electron Test 35, 173–189 (2019). https://doi.org/10.1007/s10836-019-05786-z

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