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Analysing NBTI Impact on SRAMs with Resistive Defects

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Abstract

Density’s increase in Static Random Access Memory (SRAM) has become an important concern for testing, since new types of defects, that may occur during the manufacturing process, are introduced. On the one hand, new manufacturing defects may lead to dynamic faults, which are considered one of the most important causes of test escape in deep-submicron technologies. On the other hand, the SRAM’s robustness is considered crucial, since it may affect the entire SoC. One of the most important phenomena to degrade SRAM reliability is Negative-Bias Temperature Instability (NBTI) causing the memory cells’ aging. In this context, the paper proposes to analyse the impact of NBTI on SRAM cells with resistive defects that eventually escape manufacturing test and, with aging, may generate faults over time. Finally, SPICE simulations adopting a commercial 65 nm CMOS technology library have been performed in order to estimate NBTI’s precise impact over time.

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Authors and Affiliations

  1. School of Engineering, Pontifical Catholic University of Rio Grande do Sul – PUCRS, Porto Alegre, Brazil

    M. T. Martins, G. C. Medeiros, T. Copetti, F. L. Vargas & L. M. Bolzani Poehls

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  1. M. T. Martins
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  2. G. C. Medeiros
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  3. T. Copetti
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  4. F. L. Vargas
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  5. L. M. Bolzani Poehls
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Correspondence to L. M. Bolzani Poehls.

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Responsible Editor: K. K. Saluja

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Martins, M.T., Medeiros, G.C., Copetti, T. et al. Analysing NBTI Impact on SRAMs with Resistive Defects. J Electron Test 33, 637–655 (2017). https://doi.org/10.1007/s10836-017-5685-6

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  • DOI: https://doi.org/10.1007/s10836-017-5685-6

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