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A High Performance SEU Tolerant Latch

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Abstract

This paper presents and analyzes a high performance latch tolerating single event upsets (SEU) in 45 nm CMOS technology. The internal nodes of the latch are immune to SEUs by combining Muller C-elements with dual modular redundancy and interlocked feedback. The output nodes are SEU resilient and allow a recovery to the correct logic value when an SEU occurs at output nodes. The power dissipation, propagation delay and critical charge of the proposed SEU-tolerant latch are evaluated and discussed with SPICE simulations. The simulation results show that the proposed latch achieves a better tradeoff among soft error rate, delay, power and area than previous hardened latches. On average the HPST latch requires 70.31 % area overhead, but improves the critical charge by 71.05 % and reduces the power delay product by 51.96 %. It is thus an excellent solution for applications requiring both high performance and high reliability. Monte Carlo simulation also verifies the robustness of the proposed latch in presence of process, temperature and voltage (PVT) variations.

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Acknowledgments

This work has been co-funded by National Natural Science Foundation of China (NSFC) under Grants No. (61106038, 61274036, 61371025, 61474036).

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Authors and Affiliations

  1. School of Electronic Science and Applied Physics, Hefei University of Technology, 230009, Hefei, China

    Zhengfeng Huang & Huaguo Liang

  2. Institute of Electrical Engineering and Information Technology, University of Paderborn, 33098, Paderborn, Germany

    Sybille Hellebrand

Authors
  1. Zhengfeng Huang
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  2. Huaguo Liang
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  3. Sybille Hellebrand
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Corresponding author

Correspondence to Sybille Hellebrand.

Additional information

Responsible Editor: C. Metra

A preliminary version of this paper was presented at the Conference and Exhibition on Design, Automation and Test in Europe (DATE 2014) [6].

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Huang, Z., Liang, H. & Hellebrand, S. A High Performance SEU Tolerant Latch. J Electron Test 31, 349–359 (2015). https://doi.org/10.1007/s10836-015-5533-5

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  • DOI: https://doi.org/10.1007/s10836-015-5533-5

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