Abstract
The Negative bias temperature instability (NBTI) is one of the most important reliability issues for modern CMOS technology. Accurate reliability prediction necessitates physically based models for NBTI and accurate methods for estimation of interface (∆N it ) and oxide trap (∆N ot ) generated under this degradation as well as mobility degradation (∆μ eff /μ eff0 ). In this paper, we propose an accurate approach to estimate ∆N it , ∆N ot and ∆μ eff /μ eff0 induced by NBTI degradation. This approach is based on combining on-the-fly interface trap (OTFIT) and on-the-fly threshold voltage (OTF-Vth) methods in the same time measurement setup, contrary to the classical combination where the two methods (OTFIT and OTF-Vth) are applied separately in two different measurements setups and using two transistors. In addition, the contribution of border trap to the charge pumping (CP) current in OTFIT is minimized using the high frequency signal and the scan band energy of the two combined methods is calibrated. Therefore, the data set of OTFIT and OTF-Vth can be directly comparable. The proposed approach can contribute to further understand the behavior of the NBTI degradation, especially through the mobility degradation and the threshold voltage shift contributions of interface (∆V it ) and oxide traps (∆V ot ).
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Alam MA, Kufluoglu H, Varghese D, Mahapatra SA (2007) comprehensive model for PMOS NBTI degradation: Recent progress. Microelectron Reliab 45:71–81
Ang DS, Lai SCS, Du GA, Teo ZQ, Ho TJJ, Hu YZ (2009) Effect of Hole-Trap Distribution on the Power-Law Time Exponent of NBTI. IEEE Trans Electron Devices Lett 30:751–753
Ang DS, Wang S, Du GA, Hu YZ (2008) A consistent deep-level hole trapping model for negative bias temperature instability. IEEE Trans Device Mater Rel 8:22–34
Ang D, Wang S, Ling C (2005) Evidence of two distinct degradation mechanisms from temperature dependence of negative bias stressing of the ultrathin gate p-MOSFET. IEEE Electron Devices Lett 26:906–908
Campbell JP, Lenahan PM, Krishnan AT, Krishnan S (2005) Direct observation of the structure of defect centers involved in the negative bias temperature instability. Appl Phys Lett 87:204106
Choi C, Lee JC (2011) Bulk and interface trap generation under negative bias temperature instability stress of p-chanell metal-oxide semiconductor field effect transistors with nitrogen and silicon incorporated HfO2 gate dielectrics. Appl Phys Lett 98:063504
Denais M, A. Bravaix, V. Huard, Parthasarath C, Ribes G, Perrier F et al (2004) On-the-fly characterization of NBTI in ultra-thin gate oxide PMOSFET’s, In: Proc IEDM p.109–4
Dimitrijev S, Golubović S, Župac D, Pejović M, Stojadinović N (1989) Analysis of gamma-radiation induced instability mechanisms in CMOS transistors. Sol State Electron 32:349–353
Dimitrijev S, Stojadinovic N (1987) Analysis of CMOS transistor instabilities. Sol State Electron 30:991–1003
Grasser T, Aichinger T, Reisinger H, Franco J, Wagner PJ, Nelhiebel M, et al (2010) On the ‘permanent’ component of NBTI. In Proc. Int. Integr. Reliab. Workshop pp. 2–7
Grasser T, Kaczer B (2009) Evidence that two tightly coupled mechanism are responsible for negative bias temperature instability in oxynitride MOSFETs. IEEE Trans Electron Devices 56:1056–1062
Grasser T, Kaczer B, Goes W, Aichinger T, Hehenberger P, and M. Nelhiebel (2009) ATwo-StageModel for Negative Bias Temperature Instability. In Proc. Intl. Rel. Phys. Symp. (IRPS), pp. 33–44
Grasser T, Kaczer B, Goes W, Aichinger T, Hehenberger P, Nelhiebel M (2009) Understanding negative bias temperature instability in the context of hole trapping. Microelectron Eng 86:1876–1882
Grasser T, Kaczer B, Goes W, Reisinger H, Aichinger T, Hehenberger P, Wagner PJ et al (2011) The paradigm shift in understanding the bias temperature instability: from reaction–diffusion to switching oxide traps. IEEE Trans Electron Devices 58:3652–3666
Grasser T, Wagner PJ, Reisinger H, Aichinger T, Pobegen G, Nelhiebel M, et al (2011) Analytic modeling of the bias temperature instability using capture/emission time maps, in Proc. IEDM pp. 618–621
Groeseneken G, Maes HE, Beltran N, De Keermaecker RF (1984) A reliable approach to charge pumping measurement in MOS transistors. IEEE Trans Electron Devices 3:42–53
Hamdioui S, Nicolaidis M, Gizopoulos D, Grasset A, Guido G, Bonnot P (2013) Reliability challenges ofreal-time systems in forthcoming technology nodes. Proceedings of the Conference on Design, Automationand Test in Europe, pp.129-134. doi:10.7873/DATE.2013.040
Hehenberger Ph. Aichinger Th, Grasser T, GÖs W, Triebl O, Kaczer B et al (2009) Do NBTI-Induced Interface States Show Fast Recover? A Study Using a Corrected On-The Fly Charge-Pumping Measurement Technique. In Proc. Intl. Rel. Phys. Symp (IRPS),p.1033-6.
Huard V (2010) Two independent components modeling for Negative Bias Temperature Instability. In Proc. Intl. Rel. Phys. Symp. (IRPS), pp. 33–42
Huard V, Denais M, Perrier F, Revil N, Parthasarathy C, Bravaix A et al (2005) Thorough investigation ofMOSFETs NBTI degradation. Microelectron Reliab 45:83–98
Huard V, DenaisM PC (2006) NBTI degradation: from physical mechanisms to modelling. Microelectron Reliab 46:1–23
Islam AE, Kufluoglu H, Varghese D, Mahapatra S, Alam MA (2007) Recent issues in negative bias temperature instability: Initial degradation, field-dependence of interface trap generation, and hole trapping effects and relaxation”, (Invited Paper). IEEE Trans Electron Devices 549:2143–2154
Khan S, Agbo I, Hamdioui S, Kukner H, Kaczer B, Raghavan P et al (2014) Bias Temperature Instability analysis of FinFET based SRAM Cells", Proceedings of the Conference on Design. Automation and Test in Europe, Dresden, pp 1–6
Lee JH, Wu WH, Islam AE, Alam MA, and. Oates S (2008) Separation method of hole trapping and interface trap generation and their roles in NBTI reaction–diffusion model. In Proc. Int. Reliab. Phys. Symp., pp. 745–746
Liu WJ, Liu ZY, Huang Daming, Liao CC, Zhang LF, Gan ZH et al (2007) On-The-Fly Interface Trap Measurement and Its Impact on the Understanding of NBTI Mechanism for p-MOSFETs with SiON Gate Dielectric. In: Proc IEDM p.813-3
Mahapatra S, Ahmed K, Varghese D, Islam AE, Gupta G, Madhav Let al (2007).On the Physical Mechanism of NBTI in Silicon Oxynitride p-MOSFETs: Can Differences in Insulator Processing Conditions Resolve the Interface Trap Generation versus Hole Trapping Controversy?. In Proc. Intl.Rel.Phys.Symp. (IRPS), pp.1-9
Mahapatra S, Maheta VD, Islam AE, Alam MA (2009) Isolation of NBTI Stress Generated Interface Trap and Hole-Trapping Components in PNO p-MOSFETs. IEEE Trans Electron Devices 56:236–242
Ming F, Li HD, Shen C, Yang T, Liu WJ, Liu Z (2008) Understand NBTI mechanism by developing novel measurement techniques. IEEE Trans Device Mater Rel 8:62–71
Neugroschel A, Bersuker G, Choi R, Cochrane C, Lenahan P, Heh D, et al (2006) An accurate life time analysis methodology incorporating governing NBTI mechanisms in high-k/SiO2 gate stacks. In IEDM Tech. Dig., pp. 1–4
Oates A S (2012) Reliability challenges for the continued scaling of IC technologies. IEEE Custom Integrated Circuits Conference (CICC), pp. 1–4. doi:10.1109/CICC.2012.6330658
Ogawa S, Shiono N (1995) Generalized diffusion–reaction model for the low-field charge-build up instability at the Si-SiO2 interface. Phys Rev B 51:4218–4230
Paulsen RE, Siergiej RR, French ML, White MH (1992) “Observation of near-interface oxide traps with the charge-pumping technique”. IEEE Electron Device Lett 13:627–629
Reddy V, Krishnan AT, Marshall A, Rodriguez J, Natarajan S, Rost T et al (2002) Impact of negative bias temperature instability on digital circuit reliability. In Proc. Intl.Rel.Phys.Symp. (IRPS), pp. 248 – 254. doi:10.1109/RELPHY.2002.996644
Schroder DK, Babcock JA (2003) Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing. J Appl Phys 94:1–18
Shaneyfelt MR, Fleetwood DM, Winokur PS, Schwank JR, Meisenheimer TL (1993) Effects of devices scaling and geometry on MOS radiation hardness assurance. IEEE Trans Nucl Sci 40:1678–1685
Shen C, Li MF, Foo CE, Yang T, Huang DM, Yap A, et al (2006) Characterization and physical origin of fast Vth transient in NBTI of pMOSFETs with SiON dielectric. In Proc. IEDM Tech. Dig pp. 333–336
Tahi H, Djezzar B, Benabedelmoumene A, Chenouf A (2012) On-The-Fly Extraction Method for Interface-, Oxide-Trap and Mobility Degradation Induced by NBTI Stress. In Proc Int.Int.Work (IIRW12), pp.113-116
Teo ZQ, Ang DS, Ng CM (2010) Separation of Hole Trapping and Interface-State Generation by Ultrafast Measurement on Dynamic Negative-Bias Temperature Instability. IEEE Trans Electron Devices Lett 3:656–658
Veksler D, Bersuker G, Rumyantsev S, Shur M, Park H, Young C, et al (2010) Understanding noise measurements in MOSFETs: The role of traps structural relaxation.In Proc. Intl.Rel.Phys.Symp. (IRPS), pp.73–79
Winokur PS, Shaneyfelt MR, Meisenheimen TL, Fleetwood DM (1994) Advanced qualification techniques. IEEE Trans Nucl Sci 41:8–548
ITRS Roadmap for Semiconductors, updated (2012) Process Integration Devices and Structure. http://www.itrs.net/Links/2012ITRS/Home2012.htm
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Tahanout, C., Tahi, H., Djezzar, B. et al. An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage Methods for NBTI Degradation Extraction. J Electron Test 30, 415–423 (2014). https://doi.org/10.1007/s10836-014-5464-6
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DOI: https://doi.org/10.1007/s10836-014-5464-6