Skip to main content
SpringerLink
Log in

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sensitizable PDFs in a circuit, along with all their corresponding tests. A path and test implicit method to construct such a data structure, for various path sensitization types, is presented. It uses zero-suppressed binary decision diagram (ZBDD) representations of irredundant sum-of-products (ISOPs), and requires only a polynomial number of standard ZBDD operations. Consequently, an ATPG algorithm that can exploit the properties of the proposed structure to derive tests with maximal test efficiency is presented. The obtained experimental results on the ISCAS’85 and enhanced full-scanned version of the ISCAS’89 benchmarks demonstrate that the proposed framework is scalable in terms of test efficiency and can generate compact test sets for critical PDFs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20

Similar content being viewed by others

Notes

  1. These methods estimated a lower bound on the number of unsensitizable PDFs, which can be used to indicate the completion of the ATPG process more accurately, however, they do not provide any specific guidance to the ATPG on path or test selection.

  2. Branch lines and single input gates have been explicitly represented mainly for illustration and clarification purposes. We do not use them in our implementation.

References

  1. Bhattacharya D, Agrawal P, Agrawal VD (1995) Test pattern generation for path delay faults using binary decision diagrams. IEEE Trans Comput 44(3):434–447, March

    Article  MATH  Google Scholar 

  2. Bose S, Agrawal P, Agrawal VD (1993) Generation of compact delay tests by multiple path activation. Proc ITC, pp 714–723

  3. Bryant R (1986) Graph-based algorithms for Boolean function manipulation. IEEE Trans Comput C-35(8):677–691, August

    Article  Google Scholar 

  4. Cheng KT, Chen HC (1996) Classification and identification of nonrobust untestable path delay faults. IEEE Trans CAD 15(8):845–853, August

    Google Scholar 

  5. Drechsler R, Sieling D (2001) Binary decision diagrams in theory and practice. Int J STTT No. 3, pp 112–136

  6. Heragu K, Patel JH, Agrawal VD (1997) Fast identification of untestable delay faults using implications. Proc. CAD, pp 642–647

  7. Kajihara S, Fukunaga M, Wen M, Maeda T, Hamada S, Sato Y (2005) Path delay test compaction with process variation tolerance. Proc DAC, pp 845–850, June

  8. Karayiannis D, Tragoudas S (1999) A fast non-enumerative automatic test pattern generator for path delay faults. IEEE Trans CAD 18(7):1050–1057, July

    Google Scholar 

  9. Kirkpatrick DA, Sangiovanni-Vincentelli AL (1996) Digital sensitivity: predicting signal interaction using functional analysis. Proc ICCAD, pp 536–541, November

  10. Li ZC, Brayton RK, Min Y (1997) Efficient identification of non-robustly untestable path delay faults using implications. Proc. ITC, pp 992–997

  11. McGeer PC, Saldanha A, Stephan PR, Brayton RK, Sangiovanni-Vincetelli AL (1991) Timing analysis and delay fault test generation using path recursive functions. Proc CAD, pp 180–183

  12. Michael MK, Tragoudas S (2005) Function-based compact test pattern generation for path delay faults. IEEE Trans Very Large Scale Integr 13(8):996–1001, April

    Article  Google Scholar 

  13. Minato S-I (1993) Fast generation of prime-irredundant covers from binary decision diagrams. IEICE Trans Fundam E76-A(6):976–973, June

    Google Scholar 

  14. Minato S-I (1993) Zero-suppressed BDDs for set manipulation in combinatorial problems. Proc DAC, pp 272–277

  15. Minato S-I (1996) Fast factorization method for implicit cube set representation. IEEE Trans CAD 15(3):377–384, April

    Google Scholar 

  16. Narayan A, Jain J, Fujita M, Vincentelli AS (1996) Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for boolean expressions. Proc ICCAD, pp 547–554

  17. Padmanaban S, Michael MK, Tragoudas S (2003) Exact path delay fault coverage with fundamental ZBDD operations. IEEE Trans CAD 22(3):305–316, March

    Google Scholar 

  18. Padmanaban S, Tragoudas S (2005) Efficient identification of (Critical) testable path delay faults using decisions diagrams. IEEE Trans CAD 24(1):77–87, January

    Google Scholar 

  19. Pomeranz I, Reddy SM (2003) Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans CAD 22(1):82–89, January

    Google Scholar 

  20. Pomeranz I, Reddy SM, Uppaluri P (1995) NEST: a non-enumerative test generation method for path delay faults in combinational circuits. IEEE Trans CAD 14(12):1505–1515, December

    Google Scholar 

  21. Sasao T, Butler JT (2001) Worst and best irredundant sum-of-products expressions. IEEE Trans Comput 50(9):935–948, September

    Article  MathSciNet  Google Scholar 

  22. Saxena J, Pradhan DK (1993) A method to derive compact test sets for path delay faults in combinational circuits. Proc ITC, pp 724–733

  23. Shao Y, Reddy SM, Kajihara S, Pomeranz I (2001) An efficient method to identify untestable path delay faults. Proc ITC, p 233

  24. Sharma M, Patel JH (2001) Testing of critical paths for delay faults. Proc ITC, pp 634–641

  25. Sivaraman M, Strojwas AJ (2000) Primitive path delay faults: identification and their use in timing analysis. IEEE Trans CAD 19(11):1347–1362, November

    Google Scholar 

  26. Somenzi F (1999) CUDD: CU decision diagram package. Dept. of ECE, The University of Colorado, release 2.3.0

  27. Tafertshofer P, Ganz A, Antreich KJ (2000) IGRAINE – an implication GRaph bAsed engINE for fast implication, justification, and propagation. IEEE Trans CAD 19(8):907–927, August

    Google Scholar 

  28. Wang LC, Liou JJ, Cheng KT (2004) Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans CAD 23(11):1550–1565, November

    Google Scholar 

  29. Xiang D, Li K, Fujiwara H, Sun J (2006) Generating com pact robust and non-robust tests for complete coverage of path delay faults based on stuck-at tests. Proc. ICCD, pp 446–451

Download references

Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Cyprus, Nicosia, Cyprus

    Kyriakos Christou & Maria K. Michael

  2. Department of Electrical and Computer Engineering, Southern Illinois University at Carbondale, Carbondale, USA

    Spyros Tragoudas

Authors
  1. Kyriakos Christou
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Maria K. Michael
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Spyros Tragoudas
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Maria K. Michael.

Additional information

Responsible Editor: N. A. Touba

Part of this work has appeared in “Towards finding path delay fault tests with high test efficiency using ZBDDs,” Proc. of the ICCD’2005 and in “Implicit Critical PDF Test Generation with Maximal Test Efficiency,” Proc. of DFT’2006.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Christou, K., Michael, M.K. & Tragoudas, S. On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. J Electron Test 24, 203–222 (2008). https://doi.org/10.1007/s10836-007-5020-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-007-5020-8

Keywords

Search

Navigation