Abstract
The degradation of IC interconnects due to electromigration (EM) is strongly influenced by physical defects and imperfections on interconnect traces that significantly accelerate EM damage through increased current density and elevated temperature. In this work, an IC reliability simulator is developed to incorporate the effect of these physical defects on circuit interconnect reliability. Based on a statistical defect modeling approach, circuit-level reliability with defective interconnects under EM degradation is evaluated. This has also been successfully integrated into a tool called ARET. Additionally, an approach for identifying circuit reliability hotspots has also been developed. Based on this hotspot identification, the concept of local design-for-reliability (LDFR) is proposed for improved circuit-level reliability under electromigration.
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Xuan, X., Singh, A.D. & Chatterjee, A. Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. J Electron Test 22, 471–482 (2006). https://doi.org/10.1007/s10836-006-9498-2
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DOI: https://doi.org/10.1007/s10836-006-9498-2