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A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation

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Abstract

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. The Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core. The tool can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. This is believed to be an improvement of an order of magnitude over results presented in the literature. This methodology enables the designer to tradeoff fault coverage and detection latency against area and power overhead. The design flow using the CAD tool developed is described and results for design of on-line detectors for various ISCAS89 benchmark circuits are provided. The methodology is further validated by design, fabrication, and testing of an ASIC in 0.18 μ technology.

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References

  1. S. Almukhaizim, P. Drineas, and Y. Makris “On Concurrent Error Detection with Bounded Latency in FSMs,” in Proc. DATE, 2004, pp. 596–603.

  2. F.A. Aloul, Igor L. Markov, and Karem A. Sakallah, “Efficient Gate and Input Ordering for Circuit-to-Bdd Conversion,” in Proc. International Workshop on Logic Synthesis, 2002, pp. 222–227.

  3. P. Bhowal, On Fault Diagnosis of Timed Discrete Event Systems and Hybrid Systems, PhD Dissertation, Indian Institute of Technology, Kharagpur, India, September 2002.

  4. C. Bolchini, R. Montandon, F. Salice, and D. Sciuto, “Design of VHDL Based Totally Self-Checking Finite State Machine and Data Path Descriptions,” IEEE Trans. on VLSI Systems, Vol. 8, no 1, pp. 98–102, January 2000.

    Article  Google Scholar 

  5. A. Bouloutas, G. Hart, and M. Schwartz, “On the Design of Observers for Failure Detection of Discrete Event Systems,” Proc. Network Management and Control Workshop. New York, 1989.

  6. R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Transactions on Computers, Vol. C-35, pp. 677–691, August 1986.

    Google Scholar 

  7. M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Boston: Kluwer Academic Publishers, 2000.

    Google Scholar 

  8. E.M. Clarke and O. Grumberg, “Avoiding the State Explosion Problem in Temporal Logic Model Checking,” in Proc. of the Sixth Annual ACM Symposium on Principles of Distributed Computing, 1987, pp. 294–303.

  9. D. Das and N.A. Touba, “Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-lin Codes,” IEEE VLSI Test Symposium, 1998, pp. 309–315.

  10. K. De, C. Natarajan, D. Nair, and P. Banerjee, “RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits,” IEEE Trans. Very Large Scale Integration, Vol. 2, pp. 186–195, June 1994.

    Article  Google Scholar 

  11. P. Drineas and Y. Makris, “Non-Intrusive Design of Concurrently Selftestable FSMs,” in Proc. Asian Test Symp., 2002, pp. 33– 38.

  12. P. Drineas and Y. Makris, “SPaRe: Selective Partial Replication for Concurrent Fault-Detection in FSMs,” IEEE Transactions on Instrumentation and Measurement, Vol. 52, No. 6, pp. 1729–1737, December 2003.

    Article  Google Scholar 

  13. B. Eschermann, “On Combining off-line BIST and On-Line Control-Flow Checking,” Proc. 22nd FCTS, 1992, pp. 298–305.

  14. M. Fujita, H. Fujisawa, and Y. Matsunaga, “Variable Ordering Algorithms for Ordered Binary Decision Diagrams and Their Evaluation,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol. 12, No. 1, pp. 6–12, January 1993.

    Article  Google Scholar 

  15. M.J. Geuzebroek, J.Th. van der Linden, and A.J. van de Goor, “Test Point Insertion for Compact Test Sets,” in Proc. of the IEEE Int. Test Conf., 2000, pp. 292–301.

  16. D. Gizopoulos, A. Paschalis, and Y. Zorian, “An Effective BIST Scheme for Datapaths,” Proc. IEEE International Test Conference, 1996, pp. 76–85.

  17. M. Gössel, A. Dmitiriev, V. Saposhnikov, and V. Saposhnikov, “A New Method for Concurrent Checking by Use of a 1-out-of-4 Code,” in Proc. 6th IEEE International On-Line Testing Workshop, 2000, pp. 147–152.

  18. M. Gössel and S. Graf, Error Detection Circuits (chapter 3), McGraw-Hill, 1993.

  19. S. Hashtrudi Zad, R.H. Kwong, and W.M. Wonham, “Fault Diagnosis in Timed Discrete Event System,” in Proc. 38th IEEE Conference on Decision & Control, 1998, pp. 1756–1761.

  20. S.W. Jeong, B. Plessier, G.D. Hachtel, and F. Somenzi, “Variable Ordering and Selection for FSM Traversal,” in Proc. International Conference on Computer-Aided Design, 1991, pp. 476– 479.

  21. N.K. Jha and S.J. Wang, “Design and Synthesis of Self-checking VLSI Circuits,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, pp. 878–887, June 1993.

    Article  Google Scholar 

  22. Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 2nd edition, 1978.

  23. R. Leveugle, R. Rochet, and G. Saucier, “Alternative Approaches to Fault Detection in FSM,” Defect and Fault Tolerance in VLSI Systems, 1994, pp. 271–279.

  24. R. Leveugle and G. Saucier, “Concurrent Checking in Dedicated Controllers,” in Proc. International Conference on Computer Design, 1989, pp. 124–127.

  25. R. Leveugle and G. Saucier “Optimized Synthesis of Concurrently Checked Controllers,” IEEE Transactions on Computers, Vol. 39, No. 4, pp. 419–425, April 1990.

    Article  Google Scholar 

  26. F. Lin, “Diagnosability of Discrete Event Systems and Its Applications,” Discrete Event Dyna. Syst., Vol. 4, pp. 197–212, May 1994.

    Article  Google Scholar 

  27. F. Lin, J. Markee, and B. Rado, “Design and Test of Mixed Signal Circuits: A Discrete-Event Approach,” in Proc. 32nd Conf. of Disc. Cont., 1993, pp. 246–251.

  28. A. Morozov, V.V. Saposhnikov, V. Saposhnikov, and M. Gössel, “New Self-Checking Circuits by Use of Berger-Codes,” in Proc. 6th IEEE International On-Line Testing Workshop, 2000, pp. 141–146.

  29. M. Nemani and F. Najm, “High Level Area and Power Estimation of VLSI Circuits,” in IEEE/ACM International Conference on Computer Aided Design, 1997, pp. 114–119.

  30. M. Nicolaidis, “Self-Exercising Checkers for Unified Built-In Self-Test (UBIST),” IEEE Transactions on CAD, Vol. 8, No. 3, pp. 203–218, March 1989.

    Google Scholar 

  31. M. Nicolaidis and Y. Zorian, “On-Line Testing for VLSI—A Compendium of Approaches,” Journal of Electronic Testing—Theory and Applications, Vol. 12, No. 1–2, pp. 7–20, Feb.–April 1998.

    Google Scholar 

  32. C.M. Özveren and A.S. Willsky, “Observability of Discrete Event Dynamic Systems,” Proc. IEEE Trans. Automat. Contr., Vol. 35, pp. 868–882, July 1990.

    Google Scholar 

  33. S.J. Piestrak, “Self-Checking Design in Eastern Europe,” IEEE Design and Test of Computers—Sp. Issue on Design and Test in Eastern Europe, Vol. 13, pp. 16–25, 1996.

    Google Scholar 

  34. P. Ramadge, “Observability of Discrete-Event Systems,” in Proc. 25th IEEE Conf. Decision Control, 1986, pp. 1108–1112.

  35. S.H. Robinson, “Finite State Machine Synthesis for Continuous, Concurrent Error Detection using Signature-Invariant testing,” PhD Dissertation, Carnegie Mellon University, Pittsburgh, Pennsylvania, USA, May 1992.

  36. H. Scott Robinson and John Paul Shen, “Direct Methods for Synthesis of Self-Monitoring State Machines,” in Proc. FTCS, 1992, pp. 306–315.

  37. M. Sampath, R. Sengupta, S. Lafortune, K. Sinnamohideen, and D. Teneketzis, “Diagnosability of Discrete-Event Systems,” IEEE Trans. Automat. Contr., Vol. 40, pp. 1555–1575, Sept. 1995.

    Article  Google Scholar 

  38. E.S. Sogomonyan, “Design of Built-in Self-checking Testing Circuits for Combinational Devices,” Automation and Remote Control, Vol. 35, pp. 280–289, February 1974.

    Google Scholar 

  39. E.S. Sogomonyan and M. Gössel, “A New Parity-Preserving Multi-Input Signature Analyzer,” Proc. IEEE International On-line Testing Workshop, 1995, pp. 211–215.

  40. A.P. Stroele and S. Tarnick, “Programmable Embedded Self-Testing Checkers for all Unidirectional Error-Detecting Codes,” in Proc. IEEE VLSI Test Symposium, 1999, pp. 361–369.

  41. X. Sun and M. Serra, “On-Line and Off-Line Testing with Shared Resources: A New BIST Approach,” IEEE Transactions on CAD, Vol. 16, No. 9, pp. 1045–1056, September 1997.

    Google Scholar 

  42. N.A. Touba and E.J. McCluskey, “Logic Synthesis of Multilevel Circuits with Concurrent Error Detection,” IEEE Trans. Computer-Aided Design of Integrated Circuits and System, Vol. 16, pp. 783–789, July 1997.

    Article  Google Scholar 

  43. http://www.ieee.org-IEEE 1149.1 Boundary Scan Standard.

  44. http://www.synopsys.com -“Sold” Documentation on SYNOPSYS CAD tools.

  45. C. Zeng, N. Saxena, and E. J. McCluskey, “Finite State Machine Synthesis with Concurrent Error Detection,” in Proc. Int. Test Conf., 1999, pp. 672–679.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur, West Bengal, India

    Santosh Biswas

  2. Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, India

    Siddhartha Mukhopadhyay & Amit Patra

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  1. Santosh Biswas
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  2. Siddhartha Mukhopadhyay
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  3. Amit Patra
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Correspondence to Santosh Biswas.

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Biswas, S., Mukhopadhyay, S. & Patra, A. A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation. J Electron Test 21, 503–537 (2005). https://doi.org/10.1007/s10836-005-1139-7

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