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Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication

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Abstract

Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.

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Acknowledgments

H.-Y. Chen would like to thank Yiming Zhu and Dr. Kanyu Cao’s support for the emerging memory program in the GigaDevice Semiconductor Inc. J. Sohn and H.-S. P. Wong are supported in part by the member companies of the Non-Volatile Memory Technology Research Initiative (NMTRI) industrial affiliate program at Stanford. B. Hudec, V. M. Teja, C.-C. Chang and T.-H. Hou are supported by the Ministry of Science and Technology of Taiwan under grant: 105-2119-M-009-009/104-2911-I-009-529/106-2633-E-009-001. H. B. Lv and M. Liu are supported by the MOST of China under Grant No 2016YFA0203800 and National Natural Science Foundation of China under grants No. 61522408, 61334007. J. Frascaroli, S. Brivio and S. Spiga would like to acknowledge the partial support from the European Project NeuRAM3 (grant agreement n. 687299).

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Authors and Affiliations

  1. Department of Electrical Engineering and Stanford SystemX Alliance, Stanford University, Stanford, CA, USA

    Hong-Yu Chen, Joon Sohn & H.-S. Philip Wong

  2. GigaDevice Semiconductor Inc., Beijing, China

    Hong-Yu Chen

  3. Laboratorio MDM, IMM-CNR, Via C. Olivetti 2, 20864, Agrate Brianza, Italy

    Stefano Brivio, Jacopo Frascaroli & Sabina Spiga

  4. Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, 300, Taiwan

    Che-Chia Chang, Tuo-Hung Hou, Boris Hudec & V. Mani Teja

  5. Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Science, Beijing, China

    Ming Liu & Hangbing Lv

  6. CEA Leti, Minatec Campus, Grenoble, France

    Gabriel Molas & Elisa Vianello

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Chen, HY., Brivio, S., Chang, CC. et al. Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication. J Electroceram 39, 21–38 (2017). https://doi.org/10.1007/s10832-017-0095-9

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