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T-Count Optimized Wallace Tree Integer Multiplier for Quantum Computing

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Abstract

Quantum circuits for performing an arithmetic operation are necessary for the implementation of quantum computing peripherals. An effective quantum circuit can be developed using a minimum amount of Clifford + T gates, as the implementation of Clifford + T quantum gates is more expensive than the other quantum gates. A quantum full adder (QFA) circuit for quantum computing hardware is proposed in this work. The proposed QFA circuit is optimized for T-count using a single CCNOT (Toffoli) gate. This work also focuses on implementing a quantum integer multiplication circuit using the proposed QFA to achieve better T-count savings than the existing counterparts.

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The data used for this work are available from the corresponding author upon reasonable request.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, College of Engineering and Technology, Faculty of Engineering and Technology, SRM Institute of Science and Technology, SRM Nagar, Kattankulathur 603203, Kanchipuram, Chennai, Tamil Nadu, India

    S. S. Gayathri, R. Kumar & Samiappan Dhanalakshmi

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, India

    Brajesh Kumar Kaushik

  3. Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

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  1. S. S. Gayathri
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  2. R. Kumar
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  3. Samiappan Dhanalakshmi
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  4. Brajesh Kumar Kaushik
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  5. Majid Haghparast
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Correspondence to R. Kumar.

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Gayathri, S.S., Kumar, R., Dhanalakshmi, S. et al. T-Count Optimized Wallace Tree Integer Multiplier for Quantum Computing. Int J Theor Phys 60, 2823–2835 (2021). https://doi.org/10.1007/s10773-021-04864-3

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