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Advanced methods for equivalence checking of analog circuits with strong nonlinearities

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Abstract

In this contribution two extensions for an analog equivalence checking method are proposed, enabling the checking of strongly nonlinear circuits with floating nodes such as digital library cells. Therefore, a structural recognition and mapping of eigenvalues, representing the dynamics, to circuit elements via circuit variables is presented. Additionally, the introduction of reachability analysis is significantly restricting the investigated state space to the relevant parts, avoiding false negatives. The newly introduced methods are compared to existing ones by application to industrial examples.

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References

  1. Gielen GGE (2005) Cad tools for embedded analogue circuits in mixed-signal integrated systems on chip. Comput Digit Tech IEE Proc 152(3):317–332

    Article  Google Scholar 

  2. Henzinger TA, Ho P-H (1995) Algorithmic analysis of nonlinear hybrid systems. In: CAV ’95: International conference on computer-aided verification. LNCS, vol 939(7). Springer, Berlin, pp 225–238

    Google Scholar 

  3. Dang T, Donze A, Maler O (2004) Verification of analog and mixed-signal circuits using hybrid system techniques. In: FMCAD 04: Formal methods in computer-aided design

  4. Al-Sammane G, Zaki MH, Tahar S (2007) A symbolic methodology for the verification of analog and mixed signal designs. In: DATE ’07: Proceedings of the conference on design, automation and test in Europe, pp 249–254

  5. Frehse G, Krogh BH, Rutenbar RA (2006) Verifying analog oscillator circuits using forward/backward abstraction refinement. In: DATE ’06: Proceedings of the conference on design, automation and test in Europe, pp 257–262

  6. Hartong W, Hedrich L, Barke E (2002) On discrete modeling and model checking for nonlinear analog systems. In: CAV ’02: International conference on computer-aided verification. LNCS, vol 2404. Springer, Berlin, pp 401–413

    Chapter  Google Scholar 

  7. Dastidar TR, Chakrabarti PP (2005) A verification system for transient response of analog circuits using model checking. In: VLSID ’05: International conference on VLSI design, pp 195–200

  8. Grabowski D, Olbrich M, Grimm Ch, Barke E (2008) Analog circuit simulation using range arithmetics. In: ASPDAC, pp 762–767

  9. Zaki MH, Tahar S, Bois G (2006) Formal verification of analog and mixed signal designs: survey and comparison. In: IEEE north-east workshop on circuits and systems, pp 281–284

  10. Hedrich L, Barke E (1995) A formal approach to nonlinear analog circuit verification. In: ICCAD ’95: International conference on computer aided design, pp 123–127

  11. Hartong W, Klausen R, Hedrich L (2004) Formal verification for nonlinear analog systems: approaches to model and equivalence checking. In: Drechsler R. (ed) Advanced formal verification. Kluwer Academic, Boston, pp 205–245

    Chapter  Google Scholar 

  12. Ho CW, Ruehli AE, Brennan PA (1975) The modified nodal approach to network analysis. IEEE Trans Circuits Syst 22(6):504–509

    Article  Google Scholar 

  13. Hedrich L, Hartong W (2001) Approaches to formal verification of analog circuits. In: Wambacq P (ed) Low-power design techniques and CAD tools for analog and RF integrated circuits. Kluwer Academic, Boston, pp 155–191

    Google Scholar 

  14. März R (1991) Numerical methods for differential algebraic equations. Acta Numer 141–198

  15. Van Dooren P (1979) The computation of Kronecker’s canonical form of a singular pencil. J Linear Algebra Appl 27:103–140

    Article  MATH  Google Scholar 

  16. Fortuna L, Nunnari G, Gallo A (1992) Model order reduction techniques with applications in electrical engineering. Springer, Berlin

    Google Scholar 

  17. Feldmann P, Freund RW (1995) Efficient linear circuits analysis by Pade approximation via the Lanczos process. IEEE Trans Comput-Aided Des Integr Circuits Syst 14(5):639–649

    Article  Google Scholar 

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Authors and Affiliations

  1. Electronic Design Methodology, Institute for Computer Science, Goethe University of Frankfurt/Main, Robert-Mayer-Str. 11-15, 60325, Frankfurt/Main, Germany

    Sebastian Steinhorst & Lars Hedrich

Authors
  1. Sebastian Steinhorst
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  2. Lars Hedrich
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Correspondence to Sebastian Steinhorst.

Additional information

This work was partly developed within the project VeronA (project label 01 M 3079) which is funded within the Research Program ICT 2020 by the German Federal Ministry of Education and Research (BMBF).

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Steinhorst, S., Hedrich, L. Advanced methods for equivalence checking of analog circuits with strong nonlinearities. Form Methods Syst Des 36, 131–147 (2010). https://doi.org/10.1007/s10703-009-0086-9

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