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Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies

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Abstract

SRAMs are extensively used in system-on-chip designs. Embedded SRAMs occupy majority of the die area leading to increased power consumption. Although the performance of SRAM in finer technologies has remarkably improved, still cell stability and leakage power dissipation are major concerns at deep sub-micron regime. In this paper, a low leakage SRAM cell is proposed based on source-biased inverter. The source biased inverter uses two extra transistors to mitigate the leakage power without increasing the dynamic power. The proposed inverter gives leakage power reduction of \(66.1\%\) at 100 \(^{\circ }\)C for 32 nm. The inverter is also simulated in 22 nm and 16 nm. The performance metrics like delay and power delay product are calculated. The source biased inverter is then used to replace the conventional inverters in 6T SRAM cell in 32 nm. The proposed 10T SRAM cell gives leakage power reduction of \(86.24\%\) at 100 \(^{\circ }\)C and \(90.88\%\) at 25 \(^{\circ }\)C respectively as compared to conventional 6T SRAM cell. Also, read and write bias-based assist technique is applied to improve the stability. The proposed 10T low leakage SRAM shows better stability compared to the conventional 6T SRAM cell. The performance improvement comes at the cost of four transistors. All simulations are carried out using H-spice simulator by using predictive technology models.

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Authors and Affiliations

  1. Department of ECE, Bangalore Institute of Technology, Bengaluru, India

    R. Krishna

  2. Department of ECE, M S Ramaiah Univeristy of Applied Sciences, Bengaluru, India

    Punithavathi Duraiswamy

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  1. R. Krishna
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  2. Punithavathi Duraiswamy
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Correspondence to Punithavathi Duraiswamy.

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Krishna, R., Duraiswamy, P. Low leakage 10T SRAM cell with improved data stability in deep sub-micron technologies. Analog Integr Circ Sig Process 109, 153–163 (2021). https://doi.org/10.1007/s10470-021-01870-7

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