Simulation Study and Performance Comparison of Various SRAM Cells in 32 nm CMOS Technology

Abstract

Cell stability and leakage power consumption are major concerns in SRAM cell design in deep submicron technology due to a decrease in DC supply voltage and variability in technology. This paper presents a simulation study and performance comparison of four SRAM cells, which include the traditional 6T, 7T, 8T and 9T cell implementations. In particular, the Static Noise Margin (SNM) and leakage power of each cell are analyzed in 32 nm technology. The 9T SRAM cell provides 1.05 times stronger write ability and 1.65 times stronger read stability compared to traditional 6T SRAM cell. The leakage power of 7T SRAM cell and 9T SRAM cell is 2.3$\%$ and 1.11$\%$ less compared to standard 6T SRAM cell. The effect of DC supply and temperature on SNM is also analyzed and simulation results are presented.