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Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA

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Abstract

High efficiency video coding (HEVC) is the latest video coding standard aimed to replace the H.264/AVC standard according to its high coding performance, which allows it to be mostly suitable for application in high definition videos. However, this performance is accompanied by a high computational complexity due principally to the motion estimation (ME) algorithm. As in H.264/AVC, the ME in HEVC is a highly computational demanding part that takes the largest part of the whole encoding time. Hence, many fast algorithms have been proposed in order to reduce computation, but, the majority, do not study how they can be effectively implemented by hardware. In this paper, two hardware architectures of the diamond pattern search algorithm for HEVC video coding with sequential and parallel techniques, are proposed. These architectures are based on parallel processing techniques. The sequential and parallel VHDL codes have been verified and can achieve at a high frequency on a Virtex-7 field-programmable gate-array design (FPGA) circuit. Compared to other designs, our parallel design provides better efficient implementation of available resources on FPGA. Our architecture can meet the real-time processing of the FHD @ 30 frames per second.

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References

  1. Xiong, J., Li, H., Meng, F., Wu, Q., & Ngan, K. N. (2015). Fast HEVC inter CU decision based on latent SAD estimation. IEEE Transactions on Multimedia, 17(12), 2147–2159. https://doi.org/10.1109/TMM.2015.2491018.

    Article  Google Scholar 

  2. Cheung, N. M., Fan, X., Au, O., & Kung, M. C. (2010). Video coding on multicore graphics processors. IEEE Signal Processing Magazine, 27(2), 79–89. https://doi.org/10.1109/MSP.2009.935416.

    Article  Google Scholar 

  3. Fröjdh, P., Norkin, A., & Sjöberg, R. (2013). Next generation video compression. In Ericsson Review, The Communications Technology Journal, 1–8. https://telcogroup.ru/files/materials-pdf/ericsson-hevc-h265.pdf.

  4. Sullivan, G. J., Ohm, J. R., Han, W. J., & Wiegand, T. (2012). Overview of the high efficiency video coding HEVC standard. IEEE Transactions on Circuits and Systems for Video Technology, 22(12), 1649–1668.

    Article  Google Scholar 

  5. Wiegand, T., Sullivan, G. J., Bjontegaard, G., & Luthra, A. (2003). Overview of the H.264/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560–576.

    Article  Google Scholar 

  6. Kim, J., Jun, D. S., Jeong, S., Cho, S., Choi, J. S., Kim, J., et al. (2012). An SAD-based selective bi-prediction method for fast motion estimation in high efficiency video coding. ETRI Journal, 34(5), 753–758.

    Article  Google Scholar 

  7. Yoo, H. M., & Suh, S. J. W. (2013). Fast coding unit decision algorithm based on inter and intra prediction unit termination for HEVC. In IEEE international conference on consumer electronics (ICCE) (pp. 300–301).

  8. Tham, Y. J., Ranganath, S., Ranganath, M., & Kassim, A. A. (1998). A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 8(4), 369–377.

    Article  Google Scholar 

  9. Samet, A., Souissi, N., Zouch, W., Ben Ayed, M. A., & Masmoudi, N. (2006). New horizontal diamond search motion estimation algorithm for H.264/AVC. In Second symposium on communication, control and signal processing, ISCCSP, Marrakech, Morocco (pp. 13–15).

  10. Cheung, C. H., & Po, L. M. (2002). A novel cross-diamond search algorithm for fast block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 12(12), 1168–1177.

    Article  Google Scholar 

  11. Werda, I., Chaouch, H., Samet, A., Ben Ayed, M. A., & Masmoudi, N. (2007). Optimal DSP-based motion estimation tools implementation for H.264/AVC baseline encoder. International Journal of Computer Science and Network Security, 7(5), 141–150.

    Google Scholar 

  12. Belghith, F., Kibeya, H., Loukil, H., Ben Ayed, M. A., & Masmoudi, N. (2014). A new fast motion estimation algorithm using fast mode decision for high-efficiency video coding standard. Journal of Real-Time Image Processing, 11(4), 675–691.

    Article  Google Scholar 

  13. Kibeya, H., Belghith, F., Ben Ayed, M. A., & Masmoudi, N. (2016). Fast coding unit selection and motion estimation algorithm based on early detection of zero block quantified transform coefficients for high-efficiency video coding standard. IET Image Processing, 10(5), 371–380.

    Article  Google Scholar 

  14. Nalluri, P., Alves, L. N., & Navarro, A. (2015). Complexity reduction methods for fast motion estimation in HEVC. Signal Processing: Image Communication, 39, 280–292. https://doi.org/10.1016/j.image.2015.09.015.

    Google Scholar 

  15. Khemiri, R., Bahri, N., Belghith, F., Sayedi, F. E., Atri, M. & Masmoudi, N. (2016). Fast motion estimation for HEVC video coding. In IEEEIPAS’16: International image processing applications and systems conference (pp. 1–4).

  16. Khemiri, R., Kibeya, H., Sayadi, F. E., Bahri, N., Atri, M., & Masmoudi, N. (2017). Optimisation of HEVC motion estimation exploiting SAD and SSD GPU-based implementation. IET Image Processing. https://doi.org/10.1049/iet-ipr.2017.0474.

    Google Scholar 

  17. Lu, D., Sim, D. G., & Oh, S. J. (2014). Integer-pel motion estimation for HEVC on compute unified device architecture (CUDA). IEIE Transactions on Smart Processing and Computing, 3(6), 397–403. https://doi.org/10.5573/IEIESPC.2014.3.6.397.

    Article  Google Scholar 

  18. Lu, D., Sim, D. G., Cho, K., & Oh, S. J. (2016). Fast motion estimation for HEVC on graphics processing unit (GPU). Journal of Real-Time Image Processing, 12(2), 549–562. https://doi.org/10.1007/s11554-015-0522-6.

    Article  Google Scholar 

  19. Olivares, J., Hormigo, J., Villalba, J., Benavides, I., & Zapata, E. L. (2006). SAD computation based on online arithmetic for motion estimation. Microprocessors and Microsystems, 30, 250–258.

    Article  Google Scholar 

  20. Babionitakis, K., Doumenis, G. A., Georgakarakos, G., Lentaris, G., Nakos, K., Reisis, D., et al. (2008). A real-time motion estimation FPGA architecture. Journal of Real-Time Image Processing, 3(1), 3–20. https://doi.org/10.1007/s11554-007-0070-9.

    Article  Google Scholar 

  21. Kthiri, M., Loukil, H., Werda, I., Ben Atitallah, A., Samet, A., & Masmoudi, N. (2009). Hardware implementation of fast block matching algorithm in FPGA for H.264/AVC. In IEEE 6th international multi-conference on systems, signals and devices (pp. 1–4). https://doi.org/10.1109/SSD.2009.4956714

  22. Kthiri, M., Loukil, H., Ben Atitallah, A., Kadionik, P., Dallet, D., & Masmoudi, N. (2012). FPGA architecture of the LDPS motion estimation for H.264/AVC video coding. Journal of Signal Processing Systems, 68(2), 273–285.

    Article  Google Scholar 

  23. Kthiri, M., Kadionik, P., Lévi, H., Loukil, H., Ben Atitallah, A., & Masmoudi, N. (2010). An FPGA implementation of motion estimation algorithm for H.264/AVC. In IEEE 5th international symposium on communications and mobile network (ISVC) (pp. 1–4). https://doi.org/10.1109/ISVC.2010.5654826.

  24. Rehman, S., Young, R., Chatwin, C., & Birch, P. (2009). An FPGA based generic framework for high speed sum of absolute difference implementation. European Journal of Scientific Research, 33(1), 6–29.

    Google Scholar 

  25. Nalluri, P., Alves, L. N., & Navarro, A. (2013). A Novel SAD architecture for variable block size motion estimation in HEVC video coding. In IEEE international symposium on system on chip (SoC) (pp. 1–4), Tampere.

  26. Nalluri, P., Alves, L. N., & Navarro, A. (2014). High speed SAD architectures for variable block size motion estimation in HEVC video coding. In IEEE international conference on image processing (ICIP), Paris (pp. 1233–1237).

  27. Yuan, X., Jinsong, L., Liwei, G., Zhi, Z., & Teng, R. K. F. (2013). A high performance VLSI architecture for integer-rmotion estimation in HEVC. In IEEE 10th international conference ASIC (ASICON), Shenzhen (pp. 1–4).

  28. Medhat, A., Shalaby, A., Sayed, M. S., Elsabrouty, M., & Mehdipour, F. (2014). A highly parallel SAD architecture for motion estimation in HEVC encoder. In IEEE Asia Pacific conference circuits system (APCCAS), Ishigaki (pp. 280–283). https://doi.org/10.1109/APCCAS.2014.7032774.

  29. Alcocer, E., Gutierrez, R., Lopez-Granado, O., & Malumbres, M. P. (2016). Design and implementation of an efficient hardware integer-motion estimator for an HEVC video encoder. Journal of Real-Time Image Processing. https://doi.org/10.1007/s11554-016-0572-4.

    Google Scholar 

  30. Richardson, I. E. (2002). Full search motion estimation. In I. E. G. Richardson (Ed.), Video codec design (pp. 99–101). New York: Wiley.

  31. Felipe, S., Sergio, B., Mateus, G., Luciano, A., & Julio, M. (2012). Motion vectors merging: Low complexity prediction unit decision heuristic for the inter-prediction of HEVC encoders. In IEEE international conference on multimedia and expo (pp. 657–662).

  32. Nalluri, P., Alves, L. N., & Navarro, A. (2012). Fast motion estimation algorithm for HEVC. In IEEE international conference on consumer electronics, Berlin, Germany (pp. 34–37). https://doi.org/10.1109/ICCE-Berlin.2012.6336494.

  33. Bossen, F. (2013). Common test conditions and software reference configurations. Technical report JCTVC-L1100.

  34. Jakubowski, M., & Pastuszak, G. (2013). Block-based motion estimation algorithms—A survey. Journal of Opto-Electronics Review, 21(1), 86–102. https://doi.org/10.2478/s11772-013-0071-0.

    Google Scholar 

  35. Xilinx, 7 Series FPGAs Data Sheet: Overview, DS180 (v2.2). (2016). https://www.xilinx.com/support/documentation/data_sheets/ds180_7Series_Overview.pdf.

  36. Elhamzi, W., Dubois, J., Miteran, J., & Atri, M. (2014). An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding. Journal of Real-Time Image Processing, 9(1), 19–30. https://doi.org/10.1007/s11554-012-0274-5.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Electronics and Microelectronics Laboratory, Faculty of Sciences of Monastir, University of Monastir, Environment Street, 5019, Monastir, Tunisia

    Randa Khemiri, Fatma Ezahra Sayadi & Mohamed Atri

  2. Electronics and Information Technology Laboratory, National Engineering School of Sfax, University of Sfax, Sfax, Tunisia

    Hassan Kibeya, Hassen Loukil & Nouri Masmoudi

Authors
  1. Randa Khemiri
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  2. Hassan Kibeya
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  3. Hassen Loukil
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  4. Fatma Ezahra Sayadi
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  5. Mohamed Atri
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  6. Nouri Masmoudi
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Correspondence to Randa Khemiri.

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Khemiri, R., Kibeya, H., Loukil, H. et al. Real-time motion estimation diamond search algorithm for the new high efficiency video coding on FPGA. Analog Integr Circ Sig Process 94, 259–276 (2018). https://doi.org/10.1007/s10470-017-1072-6

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  • DOI: https://doi.org/10.1007/s10470-017-1072-6

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