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Hardware-friendly HEVC motion estimation: new algorithms and efficient VLSI designs targeting high definition videos

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Abstract

In this article the spread and iterative search (S&IS) and the low density and iterative search (LD&IS) motion estimation algorithms are presented. The proposed algorithms are hardware-friendly because they have a regular number of cycles to encode a block, they have a regular memory access and the parallelism can be better explored when compared to other published solutions. The proposed algorithms were evaluated under the high efficiency video coding reference software and compared with the state-of-art enhanced predictive zonal search (EPZS) algorithm and with the well know diamond search (DS) algorithm. The designed algorithms presented better BD-rate results than DS but they presented some losses when compared to EPZS. Since EPZS is not focused in a hardware design, it presents a lot of data dependencies, a irregular memory access, a non-deterministic number of operations to encode a block and it must store motion vectors of previously encoded frames. All these features are undesirable for many applications, including those ones focused on battery powered devices. To show the efficiency of the proposed algorithms, two architectures were designed targeting these algorithms and they were synthesized for Altera Stratix 4 and for ASIC using TSMC 90 nm standard-cells technology. Synthesis results show that the architectures are capable to process HD 1080p videos, at real time, by obtaining good results in terms of hardware resources use, power consumption and processing rate when compared to related works. The ASIC implementations are able to guarantee real-time performance for high definition videos consuming 12.5 and 13.5 mW, respectively. These results are possible because S&IS and LD&IS were developed focusing on hardware design.

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References

  1. JVT, Wiegand, T., Sullivan, G., & Luthra, A. (Ed.). (2003). Draft ITU-TRecommendation and final draft international standard of joint video specification (ITU-T Rec.H.264|ISO/IEC 14496-10 AVC).

  2. JCT. (2011). Working Draft 3 of high-efficiency video coding. JCTVC-E603.

  3. Cheng, Y., et al. (2009). An H.264 spatio-temporal hierarchical fast motion estimation algorithm for high-definition video. IEEE International Symposium on Circuits and Systems (ISCAS), 2009, 880–883.

    Google Scholar 

  4. Kuhn, P. (1999). Algorithms, complexity analysis and VLSI architectures for MPEG-4 motion estimation (Vol. 2). Amsterdam: Kluwer Academic Publishers.

    Book  MATH  Google Scholar 

  5. Bhaskaran, V., & Konstantinides, K. (1999). Image and video compression standards: Algorithms and architectures (2nd ed.). Boston: Kluwer Academic Publishers.

    Google Scholar 

  6. Walter, F., Diniz, C., & Bampi, S. (2012). Synthesis and comparison of low-power high-throughput architectures for SAD calculation. Analog Integrated Circuits and Signal Processing, 73, 873–884.

    Article  Google Scholar 

  7. Sanchez, G., Correa, M., Noble, D., Porto, M., Bampi, S., & Agostini, L. (2012). Hardware design focusing in the tradeoff cost versus quality for the H.264/AVC fractional motion estimation targeting high definition videos. Analog Integrated Circuits and Signal Processing, 73, 931–944.

    Article  Google Scholar 

  8. Zhu, S., & Ma, K. (2000). A new diamond search algorithm for fast block-matching motion estimation. IEEE Transactions on Image Processing, 9(2), 287–290.

    Article  MathSciNet  Google Scholar 

  9. Zhu, C., Lin, X., & Chau, L. (2002). Hexagon-based search pattern for fast block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 12(5), 349–355.

    Article  Google Scholar 

  10. Jing, X., & Chau, L. (2004). An efficient three-step search algorithm for Block motion estimation. IEEE Transactions on Multimedia, 6(3), 435–438.

    Article  Google Scholar 

  11. Chok-Kwan, C., & Lai-Man, P. (2000). Normalized partial distortion search algorithm for block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 10(3), 417–422.

    Article  Google Scholar 

  12. Porto, M., et al. (2011). An efficient ME architecture for high definition videos using the new MPDS algorithm. In ACM Symposium on Integrated Circuits and Systems Design (SBCCI) (pp. 119–124).

  13. Tourapis, A. (2002). Enhanced predictive zonal search for single and multiple frame motion estimation. In Proceedings of Visual Communications and Image Processing (VCIP) (pp. 1069–1079).

  14. Sanchez, G., et al. (2012). Spread and iterative search: A high quality motion estimation algorithm for high definition videos and its VLSI design. In IEEE International Conference on Multimedia and Expo (ICME) (pp. 1079–1084).

  15. Sanchez, G., et al. (2013). A fast hardware-friendly motion estimation algorithm and its VLSI design for real time ultra high definition applications. In IEEE Latin American Conference on Circuits and Systems (LASCAS).

  16. Joint Collaborative Team on Video Coding (JCT-VC) (2011). High Efficiency Video Coding (HEVC) Test Model 5 (HM 5) Reference Software [Online]. https://hevc.hhi.fraunhofer.de/svn/svn_HEVCSoftware/branches/HM-5.0-dev/. Accessed May 2013.

  17. Lu, J., et al. (2007). An epipolar geometry-based fast disparity estimation algorithm for multiview image and video coding. IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 17(6), 737–750.

    Article  Google Scholar 

  18. Lai, Y., et al. (2010). Hybrid parallel motion estimation architecture based on fast top-winners search algorithm. IEEE Transactions on Consumer Electronics (TCE), 56(3), 1837–1842.

    Article  Google Scholar 

  19. Yin, H., et al. (2010). A hardware-efficient multi-resolution block matching algorithm and its VLSI architecture for high definition MPEG-like video encoders. IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), 20(9), 1242–1254.

    Article  Google Scholar 

  20. Cetin, M., et al. (2011). An adaptive true motion estimation algorithm for frame rate conversion of high definition video and its hardware implementations. IEEE Transactions on Consumer Electronics (TCE), 57(2), 923–931.

    Article  MathSciNet  Google Scholar 

  21. Kao, C., Wu, C., & Lin, Y. (2010). A high-performance three-engine architecture for H.264/AVC fractional motion estimation. IEEE Transactions on Very Large Scale Integration Systems, 18(4), 662–666.

    Article  Google Scholar 

  22. Tasdizen, O., et al. (2009). Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation. IEEE Transactions on Consumer Electronics, 55(3), 1645–1653.

    Article  Google Scholar 

  23. Vanne, J., et al. (2009). A configurable motion estimation architecture for block-matching algorithms. IEEE Transactions on Circuits and Systems for Video Technology, 19(4), 446–476.

    Article  Google Scholar 

  24. Bjontegaard, G., (2001, April). Calculation of average PSNR differences between RD curves. In VCEG-M33, ITU-T SG16/Q6 VCEG, 13th VCEG Meeting, Austin, USA.

  25. Altera Corporation. Altera: The Programmable Solutions Company. Available at www.altera.com. Accessed May 2013.

  26. Chen, C.-H., et al. (2006). Level C+ data reuse scheme for motion estimation with corresponding coding orders. IEEE TCSVT, 16(4), 553–558.

    Google Scholar 

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Authors and Affiliations

  1. Group of Architectures and Integrated Circuits, Federal University of Pelotas, Pelotas, Brazil

    Gustavo Sanchez, Bruno Zatt, Marcelo Porto & Luciano Agostini

Authors
  1. Gustavo Sanchez
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  2. Bruno Zatt
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  3. Marcelo Porto
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  4. Luciano Agostini
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Correspondence to Gustavo Sanchez.

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Sanchez, G., Zatt, B., Porto, M. et al. Hardware-friendly HEVC motion estimation: new algorithms and efficient VLSI designs targeting high definition videos. Analog Integr Circ Sig Process 82, 135–146 (2015). https://doi.org/10.1007/s10470-014-0342-9

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  • DOI: https://doi.org/10.1007/s10470-014-0342-9

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