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Design methodology for low-jitter differential clock recovery circuits in high performance ADCs

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Abstract

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits (<100 fsrms) for high-performance ADCs. The key ideas of the design methodology are: (a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, (b) based on this parameterization, carrying out a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100 fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8 V 0.18 µm and 1.2 V 90 nm). Post-layout simulation results for a case of study with typical jitter of 68 fs for a 1.8 V 80 dB-SNDR 100Msps Pipeline ADC application are also shown as demonstrator.

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References

  1. Lee, H.-S., & Sodini, C. G. (2008). Analog-to-Digital Converters: Digitizing the Analog World. Proceedings of the IEEE, 96(2), 323–334.

    Article  Google Scholar 

  2. Brannon, B., (2004) “Sampled systems and the effects of clock phase noise and jitter”, Analog devices application note, AN-756.

  3. Zanchi, A., & Tsay, F. (2005). A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter. IEEE Journal of Solid-State Circuits, 40(6), 1225–1237.

    Article  Google Scholar 

  4. Cheng L., Yang H., Luo L., and Ren J., (2010) “Analysis and design of low-jitter clock driver for wideband ADC,” Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on, Shanghai. pp. 515–517.

  5. Unekawa Y. et al. (1996) “A 5 Gb/s 8/spl times/8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface,” Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International, San Francisco, pp. 118–119.

  6. Boni, A., Pierazzi, A., & Vecchi, D. (2001). LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS. IEEE Journal of Solid-State Circuits, 36(4), 706–711.

    Article  Google Scholar 

  7. Núñez, J., Ginés, A. J., Peralías, E. J., & Rueda, A., (2015) “Low-jitter differential clock driver circuits for high-performance high-resolution ADCs,” Design of Circuits and Integrated Systems (DCIS), 2015 Conference on, Estoril, pp. 1–4.

  8. Alpaydin, G., Balkir, S., & Dundar, G. (2003). An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Transactions on Evolutionary Computation, 7(3), 240–252.

    Article  Google Scholar 

  9. Barros, M., Guilherme, J., & Horta, N. (2010). Analog circuits optimization based on evolutionary computation techniques. Integration, the VLSI Journal, 43(1), 136–155.

    Article  MATH  Google Scholar 

  10. Deb, K., Pratap, A., Agarwal, S., & Meyarivan, T. (2002). A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Transactions on Evolutionary Computation, 6(2), 182–197.

    Article  Google Scholar 

  11. Medeiro, F., Pérez-Verdú, B., & Rodríguez-Vázquez, A. (1998). Top-Down Design of High-Performance Sigma-Delta Modulators. Dordrecht: Kluwer Academic Publishers. ISBN 0-7923-8352-4.

    Google Scholar 

  12. Liu, B., Fernandez, F. V., & Gielen, G. G. E. (2011). Efficient and accurate statistical analog yield optimization and variation-aware circuit sizing based on computational intelligence techniques. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 30(6), 793–805.

    Article  Google Scholar 

  13. Goes, J., Vital, J. C., & Franca, J. (2001). Systematic Design for Optimisation of Pipelined ADCs. Dordrecht: Kluwer Academic Publisher. ISBN 0792372913.

    Google Scholar 

  14. Núñez, J., Ginés, A. J., Peralías, E. J., & Rueda, A. (2015). “An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs,” Circuits & Systems (LASCAS), IEEE 6th Latin American Symposium on. Montevideo, 2015, 1–4.

    Google Scholar 

  15. IEEE Standards, “IEEE standard for terminology and test methods for analog-to-digital converters,” IEEE Std 1241-2000, 2001.

  16. Demir, A., & Sangiovanni-Vincentelli, A. (1997). Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems. Dordrecht: Kluwer Academic Publishers. ISBN 10: 0792380371.

    MATH  Google Scholar 

  17. Phillips, J., and Kundert, K., (2000) “Noise in mixers, oscillators, samplers, and logic an introduction to cyclostationary noise,” Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000, Orlando, pp. 431–438.

  18. K. Kunder, K., (2015) “Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers”, v.4i, available at http://www.designers-guide.org/analysis.

  19. Hegazi, E., Sjoland, H., & Abidi, A. A. (2001). A filtering technique to lower LC oscillator phase noise. IEEE Journal of Solid-State Circuits, 36(12), 1921–1930.

    Article  Google Scholar 

  20. European Space Agency (ESA) contract: 4000108445-13-NL-RA “ADC 16 bits”.

  21. Maxim Integrated Products: Application Note 3631, “Random Noise Contribution to Timing Jitter—Theory and Practice”, available at http://www.maximintegrated.com/an3631.

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Acknowledgments

This work was supported in part by the Spanish Government projects TEC2015-68448-R cofinanced by the European FEDER program, and by the European Space Agency (ESA) contract: 4000108445-13-NL-RA “ADC 16bits”.

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Authors and Affiliations

  1. Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Av. Américo Vespucio s/n, 41092, Seville, Spain

    Juan Núñez, Antonio J. Ginés, Eduardo J. Peralías & Adoración Rueda

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  1. Juan Núñez
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  2. Antonio J. Ginés
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  3. Eduardo J. Peralías
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  4. Adoración Rueda
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Correspondence to Juan Núñez.

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Núñez, J., Ginés, A.J., Peralías, E.J. et al. Design methodology for low-jitter differential clock recovery circuits in high performance ADCs. Analog Integr Circ Sig Process 89, 593–609 (2016). https://doi.org/10.1007/s10470-016-0870-6

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  • DOI: https://doi.org/10.1007/s10470-016-0870-6

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