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Fully integrated Doherty power amplifier in CMOS 65 nm with constant PAE in Backoff

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Abstract

Design methodology and measurements results are presented for a Doherty power amplifier (DPA) fully integrated with its input/output network matching and choke inductances in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 to 2.6 GHz show constant PAE performance starting in 20 % level up to 24 % with a maximum output power of 23.4 dBm. The circuit is fully described with all components values and layout details for further reproduction. Performance graphs showing the active load-pull effect, sub-amplifiers behavior and constant PAE prove that it is a real DPA with all effects as known by the theory. The circuit is composed by only lumped components, each sub-amplifier has cascode topology and their input/output networks are optimized to save die area and to produce a constant PAE.

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Acknowledgments

Authors would like to thank STMicroelectronics and CAPES/COFECUB program.

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Brasília, Brasília, Brazil

    Marcos L. Carneiro & Paulo Henrique Portela de Carvalho

  2. Laboratory IMS, CNRS UMR 5218, IPB, University of Bordeaux, 351crs de la Libération, 33405, Talence, France

    Eric Kerhervé & Nathalie Deltimple

  3. STMicroelectronics, Crolles, France

    Didier Belot

Authors
  1. Marcos L. Carneiro
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  2. Eric Kerhervé
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  3. Nathalie Deltimple
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  4. Didier Belot
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  5. Paulo Henrique Portela de Carvalho
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Correspondence to Marcos L. Carneiro.

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Carneiro, M.L., Kerhervé, E., Deltimple, N. et al. Fully integrated Doherty power amplifier in CMOS 65 nm with constant PAE in Backoff. Analog Integr Circ Sig Process 82, 89–97 (2015). https://doi.org/10.1007/s10470-014-0451-5

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  • DOI: https://doi.org/10.1007/s10470-014-0451-5

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